CAT24C256LI

CAT24C256 256-Kb I2C CMOS Serial EEPROM FEATURES DEVICE DESCRIPTION ■ Supports Standard and Fast I2C Protocol The CAT24C256 is a 256-Kb Serial CMOS EEPROM, internally organized as 32,768 words of 8 bits each. ■ 1.8V to 5.5V Supply Voltage Range It features a 64-byte page write buffer and supports both the Standard (100kHz) as well as Fast (400kHz) I2C protocol. ■ 64-Byte Page Write Buffer ■ Hardware Write Protection for entire memory ■ Schmitt Triggers and Noise Suppression Filters Write operations can be inhibited by taking the WP pin High (this protects the entire memory). on I2C Bus Inputs (SCL and SDA). ■ Low power CMOS technology External address pins make it possible to address up to eight CAT24C256 devices on the same bus. ■ 1,000,000 program/erase cycles ■ 100 year data retention ■ Industrial temperature range ■ RoHS-compliant 8-pin PDIP, SOIC, TSSOP and 8-pad TDFN packages For Ordering Information details, see page 15. PIN CONFIGURATION FUNCTIONAL SYMBOL PDIP (L) SOIC (W, X) TSSOP (Y) TDFN (ZD2) VCC A0 1 8 VCC A1 2 7 WP A2 VSS 3 6 SCL 4 5 SDA SCL A2, A1, A0 For the location of Pin 1, please consult the corresponding package drawing. CAT24C256 SDA WP VSS PIN FUNCTIONS A0, A1, A2 Device Address SDA Serial Data SCL Serial Clock WP Write Protect VCC Power Supply VSS Ground © 2008 SCILLC. All rights reserved Characteristics subject to change without notice * Catalyst carries the I2C protocol under a license from the Philips Corporation. 1 Doc. No. MD-1104, Rev. G CAT24C256 ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature Voltage on Any Pin with Respect to -65°C to +150°C Ground(2) -0.5 V to +6.5 V RELIABILITY CHARACTERISTICS(3) Symbol (4) NEND TDR Parameter Min Units Endurance 1,000,000 Program/ Erase Cycles 100 Years Data Retention D.C. OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Test Conditions ICC Supply Current ISB Min Max Units Read or Write at 400kHz 1 mA Standby Current All I/O Pins at GND or VCC 1 μA IL I/O Pin Leakage Pin at GND or VCC 1 μA VIL Input Low Voltage VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0mA 0.4 V VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0mA 0.2 V Max Units -0.5 PIN IMPEDANCE CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Conditions CIN(3) SDA I/O Pin Capacitance VIN = 0V 8 pF CIN(3) Input Capacitance (other pins) VIN = 0V 6 pF WP Input Current (CAT24C256 Rev. C - New Product) VIN < VIH, VCC = 5.5V 200 VIN < VIH, VCC = 3.3V 150 VIN < VIH, VCC = 1.8V 100 (5) IWP VIN > VIH Min μA 1 Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC = 5V, 25°C (5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. The variable WP input impedance is available only for Die Rev. C, New Product. Doc. No. MD-1104, Rev. G 2 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24C256 A.C. CHARACTERISTICS(1) VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Standard Symbol FSCL tHD:STA Parameter Min Clock Frequency Max Fast Min 100 START Condition Hold Time Max Units 400 kHz 4 0.6 μs tLOW Low Period of SCL Clock 4.7 1.3 μs tHIGH High Period of SCL Clock 4 0.6 μs 4.7 0.6 μs tSU:STA START Condition Setup Time tHD:DAT Data In Hold Time 0 0 μs tSU:DAT Data In Setup Time 250 100 ns tR(2) SDA and SCL Rise Time 1000 300 ns tF(2) SDA and SCL Fall Time 300 300 ns tSU:STO 4 0.6 μs 4.7 1.3 μs STOP Condition Setup Time tBUF Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time Ti(2) Noise Pulse Filtered at SCL and SDA Inputs 3.5 100 0.9 100 100 μs ns 100 ns tSU:WP WP Setup Time 0 0 μs tHD:WP WP Hold Time 2.5 2.5 μs tWR tPU(2, 3) Write Cycle Time 5 5 ms Power-up to Ready Mode 1 1 ms Notes: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands. A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC Input Rise and Fall Times ≤ 50ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.5 x VCC Output Load Current Source: IOL = 3mA (VCC ≥ 2.5V); IOL = 1 mA (VCC < 2.5V); CL = 100pF © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 3 Doc No. MD-1104, Rev. G CAT24C256 POWER-ON RESET (POR) I2C BUS PROTOCOL The CAT24C256 Die Rev. C incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the 2wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR feature protects the device against ‘brown-out’ failure following a temporary loss of power. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 1). PIN DESCRIPTION SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. START SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake-up’ call to all receivers. Absent a START, a Slave will not respond to commands. A0, A1 and A2: The Address pins accept the device address. These pins have on-chip pull-down resistors. STOP WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. This pin has an on-chip pull-down resistor. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when following a Write command) or sends the Slave into standby mode (when following a Read command). FUNCTIONAL DESCRIPTION Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations (Figure 2). The next 3 bits, A2, A1 and A0, select one of 8 possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. The CAT24C256 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24C256 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2. Doc. No. MD-1104, Rev. G Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 3). The Slave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. If the Master acknowledges the data, then the Slave continues transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by sending a STOP to the Slave. Bus timing is illustrated in Figure 4. 4 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24C256 Figure 1. Start/Stop Timing SCL SDA START CONDITION STOP CONDITION Figure 2. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W DEVICE ADDRESS Figure 3. Acknowledge Timing BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACK SETUP (≥ tSU:DAT) START ACK DELAY (≤ tAA) Figure 4. Bus Timing tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 5 Doc No. MD-1104, Rev. G CAT24C256 WRITE OPERATIONS Byte Write In Byte Write mode the Master sends a START, followed by Slave address, two byte address and data to be written (Figure 5). The Slave acknowledges all 4 bytes, and the Master then follows up with a STOP, which in turn starts the internal Write operation (Figure 6). During internal Write, the Slave will not acknowledge any Read or Write request from the Master. Page Write The CAT24C256 contains 32,768 bytes of data, arranged in 512 pages of 64 bytes each. A two byte address word, following the Slave address, points to the first byte to be written. The most significant bit of the address word is ‘don’t care’, the next 9 bits identify the page and the last 6 bits identify the byte within the page. Up to 64 bytes can be written in one Write cycle (Figure 7). The internal byte address counter is automatically incremented after each data byte is loaded. If the Master transmits more than 64 data bytes, then earlier bytes will be overwritten by later bytes in a ‘wrap-around’ fashion (within the selected page). The internal Write cycle starts immediately following the STOP. Acknowledge Polling Acknowledge polling can be used to determine if the CAT24C256 is busy writing or is ready to accept commands. Polling is implemented by interrogating the device with a ‘Selective Read’ command (see READ OPERATIONS). The CAT24C256 will not acknowledge the Slave address, as long as internal Write is in progress. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C256. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 8). If the WP pin is HIGH during the strobe interval, the CAT24C256 will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24C256 is shipped erased, i.e., all bytes are FFh. Doc. No. MD-1104, Rev. G 6 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24C256 Figure 5. Byte Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 S A C K S T O P DATA P * A C K A C K A C K * = Don't Care Bit Figure 6. Write Cycle Timing SCL 8th Bit Byte n SDA ACK tWR START CONDITION STOP CONDITION ADDRESS Figure 7. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 S A C K DATA DATA n S T O P DATA n+63 P * A C K A C K A C K A C K A C K A C K * = Don't Care Bit Figure 8. WP Timing ADDRESS BYTE DATA BYTE 1 8 a7 a0 9 1 8 d7 d0 SCL SDA tSU:WP WP tHD:WP © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 7 Doc No. MD-1104, Rev. G CAT24C256 READ OPERATIONS Immediate Address Read In standby mode, the CAT24C256 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If that ‘previous’ byte was the last byte in memory, then the address counter will point to the 1st memory byte, etc. When, following a START, the CAT24C256 is presented with a Slave address containing a ‘1’ in the R/W bit position (Figure 9), it will acknowledge (ACK) in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. The Master can stop further transmission by issuing a NoACK, followed by a STOP condition. Selective Read The Read operation can also be started at an address different from the one stored in the internal address counter. The address counter can be initialized by performing a ‘dummy’ Write operation (Figure 10). Here the START is followed by the Slave address (with the R/W bit set to ‘0’) and the desired two byte address. Instead of following up with data, the Master then issues a 2nd START, followed by the ‘Immediate Address Read’ sequence, as described earlier. Sequential Read If the Master acknowledges the 1st data byte transmitted by the CAT24C256, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Figure 11). If the end of memory is reached during sequential Read, then the address counter will ‘wrap-around’ to the beginning of memory, etc. Sequential Read works with either ‘Immediate Address Read’ or ‘Selective Read’, the only difference being the starting byte address. Doc. No. MD-1104, Rev. G 8 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24C256 Figure 9. Immediate Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS S P A C K N O DATA A C K 8 SCL 9 8th Bit SDA DATA OUT NO ACK STOP Figure 10. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS A15 – A 8 A7 – A 0 * S S T O P DATA S A C K * = Don't Care Bit SLAVE ADDRESS A C K P A C K A C K N O A C K Figure 11. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K N O A C K © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 9 Doc No. MD-1104, Rev. G CAT24C256 PACKAGE OUTLINE DRAWINGS PDIP 8-Lead 300 mils (L) PDIP 8-Lead 300mils (L) SYMBOL MIN NOM A A1 MAX 5.33 0.38 A2 2.92 3.30 b 0.36 0.46 4.95 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 e 2.54 BSC E1 6.10 eB 7.87 L 2.92 6.35 7.11 10.92 3.30 3.80 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. Doc. No. MD-1104, Rev. G 10 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24C256 SOIC 8-Lead 150 mils (W) E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 MAX E 5.80 6.20 E1 3.80 4.00 e PIN # 1 IDENTIFICATION NOM 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf Notes: (1) Complies with JEDEC specification MS-012 dimensions. (2) All linear dimensions are in millimeters. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 11 Doc No. MD-1104, Rev. G CAT24C256 SOIC 8-Lead 208 mils (X) SYMBOL MIN NOM A E1 E MAX 2.03 A1 0.05 0.25 b 0.36 0.48 c 0.19 0.25 D 5.13 5.33 E 7.75 8.26 E1 5.13 5.38 e 1.27 BSC L 0.51 0.76 θ 0º 8º PIN#1 IDENTIFICATION TOP VIEW D A e b θ L A1 SIDE VIEW c END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf Notes: (1) Complies with EIAJ specification. (2) All linear dimensions are in millimeters. Doc. No. MD-1104, Rev. G 12 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24C256 TSSOP 8-Lead 4.4mm (Y) b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 A2 0.80 b 0.19 c 0.09 D 2.90 0.15 0.90 1.05 0.30 0.20 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.65 BSC L 1.00 REF L1 0.50 θ1 0° 0.60 0.75 8° e TOP VIEW D A2 A c θ1 A1 L1 SIDE VIEW L END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf Notes: (1) All dimensions are in milimiters. Angles in degrees (2) Complies with JEDEC MO-153. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 13 Doc No. MD-1104, Rev. G CAT24C256 TDFN 8-Pad 3 x 4.9mm (ZD2) D A DETAIL A DAP SIZE 2.6 x 3.3mm E E2 PIN #1 IDENTIFICATION A1 PIN #1 IDENTIFICATION D2 TOP VIEW SYMBOL MIN SIDE VIEW NOM A 0.70 0.75 0.80 0.00 0.02 0.05 A2 0.45 0.55 0.65 b A1 A3 FRONT VIEW 0.20 REF 0.25 0.30 D 2.90 3.00 3.10 0.90 1.00 1.10 E 4.80 4.90 5.00 E2 0.90 1.00 1.10 e b 0.35 D2 L A2 A MAX A1 A3 BOTTOM VIEW L e 0.65 TYP 0.50 0.60 0.70 DETAIL A For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf Notes: (1) All dimensions are in milimiters. (2) Complies with JEDEC MO-229. Doc. No. MD-1104, Rev. G 14 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24C256 ORDERING INFORMATION Prefix CAT Company ID Device # Suffix 24C256 Product Number L: W: X: Y: ZD2: W I — G Temperature Range I = Industrial (-40°C to +85°C) Package PDIP SOIC, JEDEC SOIC, EIAJ(4) TSSOP TDFN (3x4.9mm)(5) T3 Tape & Reel T: Tape & Reel 2: 2000/Reel(4)(5) 3: 3000/Reel Lead Finish Blank: Matte-Tin(4) G: NiPdAu Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT24C256WI-GT3 (SOIC-JEDEC, Industrial Temperature, NiPdAu, Tape & Reel). (4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT24C256XI-T2. (5) The TDFN 3x4.9mm (ZD2) package is available in 2000 pcs/reel, i.e., CAT24C256ZD2I-GT2. (6) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 15 Doc No. MD-1104, Rev. G CAT24C256 REVISION HISTORY Date Revision Comments 10/07/05 A 11/16/05 B 02/02/06 C Update Ordering Information D Update Package Outlines. Add SOIC, EIAJ Package Outlines Update A.C. Characteristics. Add A.C. Test Conditions Update Figures 1, 3 and 4 Delete Package Marking. Deleted Tape and Reel Update Ordering Information 05/08/07 E Update Features/Packages Update Pin Configuration Update Pin Impedance Characteristics Add Power-On Reset (POR) text Update Hardware Write Protection Add WP Timing (Figure 8) (Renumbered Figures 9 & 11) Add 8-Lead TSSOP Package Outline Add 8-pad TDFN 3x4.9mm Package Outline Updated Ordering Information 08/15/07 F Updated PDIP, SOIC, TSSOP, and TDFN Package Outline Drawings 12-Oct-08 G Updated SOIC 8L, 208mil, Package Outline Drawing Change logo and fine print to ON Semiconductor 01/12/07 Doc. No. MD-1104, Rev. G Initial Issue Update Ordering Information Add Tape and Reel Specifications 16 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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