CAT25AM02C8CTR

CAT25AM02 2 Mb SPI Serial CMOS EEPROM Description The CAT25AM02 is a 2M−bit Serial CMOS EEPROM device internally organized as 256Kx8 bits. This features a 256−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAT25AM02 device. The device features software and hardware write protection, including partial as well as full array protection. On−Chip ECC (Error Correction Code) makes the device suitable for high reliability applications. The CAT25AM02 device is designed for ultra−low power consumption, targeting real−time data logging applications, hearing aids and other medical devices and battery operated applications. http://onsemi.com WLCSP−8 C8A, C8C SUFFIXES CASE 567GV PIN CONFIGURATION Features • • • • • • • • • • • • • Pin 1 5 MHz SPI Compatible Supply Voltage Range: 1.6 V to 3.6 V SPI Modes (0,0) & (1,1) 256−byte Page Write Buffer Additional Identification Page with Permanent Write Protection Self−timed Write Cycle Hardware and Software Protection Block Write Protection – Protect 1/4, 1/2 or Entire EEPROM Array Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention WLCSP 8−ball Package, and Die Sales These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant VCC VCC HOLD SCK WLCSP (C8A, C8C) (Top View) PIN FUNCTION Pin Name Chip Select SO Serial Data Output WP Write Protect VSS Ground Serial Data Input SCK CS HOLD WP VCC HOLD Function CS SI SO SO WP VSS SI SI CAT25AM02 CS Serial Clock Hold Transmission Input Power Supply SCK ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. VSS Figure 1. Functional Symbol © Semiconductor Components Industries, LLC, 2014 February, 2014 − Rev. 1 1 Publication Order Number: CAT25AM02/D CAT25AM02 MARKING DIAGRAM EA2M ALYWG G (WLCSP−8) EA2M = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units 0 to +85 °C Storage Temperature –10 to +90 °C Voltage on any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V Operating Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 5) Parameter Symbol NEND (Notes 2, 3) TDR Endurance Data Retention Min Units 1,000,000 Program/Erase Cycles 100 Years 2. Page Mode, VCC = 5 V, 25°C. 3. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes located at addresses 4N, 4(N+1), 4(N+2), 4(N+3), in order to benefit from the maximum number of write cycles. Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.6 V to 3.6 V, TA = 0°C to +70°C, unless otherwise specified.) Symbol Max Units Supply Current VCC = 3.6 V, SO open, fCLK = 5 MHz 0.8 mA (Read Mode) VCC = 1.6 V, SO open, fCLK = 5 MHz 0.4 Supply Current VCC = 3.6 V 1.0 (Write Mode) VCC = 1.6 V 0.7 ISB1 (Note 4) Standby Current VIN = GND or VCC, CS = VCC, WP = VCC, HOLD = VCC ISB2 (Note 4) Standby Current VIN = GND or VCC, CS = VCC, WP = GND, HOLD = GND Input Leakage Current VIN = GND or VCC −1 ILO Output Leakage Current CS = VCC, VOUT = GND or VCC VIL1 Input Low Voltage VIH1 ICCR ICCW Parameter Test Conditions Min mA 1 mA 3 mA 1 mA −1 1 mA VCC ≥ 2.5 V −0.5 0.3 x VCC V Input High Voltage VCC ≥ 2.5 V 0.7 x VCC VCC + 0.5 V VIL1 Input Low Voltage VCC < 2.5 V −0.5 0.25 x VCC V 0.75 x VCC VCC + 0.5 V 0.4 V IL VIH1 Input High Voltage VCC < 2.5 V VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA VOH1 Output High Voltage VCC ≥ 2.5 V, IOH = −1.6 mA VOL2 Output Low Voltage VCC < 2.5 V, IOL = 150 mA VOH2 Output High Voltage VCC < 2.5 V, IOH = −100 mA VCC − 0.8 V 0.2 VCC − 0.2 V V 4. When not driven, the WP and HOLD inputs are pulled up to VCC internally. For noisy environments, when the pin is not used, it is recommended the WP and HOLD input to be tied to VCC, either directly or through a resistor. http://onsemi.com 2 CAT25AM02 Table 4. PIN CAPACITANCE (Note 5) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V) Test Symbol COUT CIN Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) Min Typ Max Units VOUT = 0 V 8 pF VIN = 0 V 8 pF 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. Table 5. A.C. CHARACTERISTICS (VCC = 1.6 V to 3.6 V, TA = 0°C to +70°C, unless otherwise specified.) (Note 6) Parameter Symbol Min Max Units 5 MHz fSCK Clock Frequency DC tSU Data Setup Time 20 ns tH Data Hold Time 20 ns tWH SCK High Time 75 ns tWL SCK Low Time 75 ns tLZ HOLD to Output Low Z 50 ns tRI (Note 7) Input Rise Time 2 ms tFI (Note 7) Input Fall Time 2 ms tHD HOLD Setup Time 0 tCD HOLD Hold Time 10 tV Output Valid from Clock Low ns ns 75 0 ns tHO Output Hold Time ns tDIS Output Disable Time 50 ns tHZ HOLD to Output High Z 100 ns tCS CS High Time 80 ns tCSS CS Setup Time 60 ns tCSH CS Hold Time 60 ns tCNS CS Inactive Setup Time 60 ns tCNH CS Inactive Hold Time 60 ns tWPS WP Setup Time 20 ns tWPH WP Hold Time 20 ns tWC (Note 8, 10) Write Cycle Time 10 ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 6. POWER−UP TIMING (Notes 7, 9) Symbol tPUR, tPUW Parameter Min Power−up to Read / Write Operation Max Units 0.1 ms 6. AC Test Conditions: Input Pulse Voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 10 ns Input and output reference voltages: 0.5 VCC Output load: current source IOL max/IOH max; CL = 30 pF 7. This parameter is tested initially and after a design or process change that affects the parameter. 8. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. 9. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 10. The tWC time can be set by the user to allow faster internal writes (max 3 ms) by setting the tWC bit from the Status Register. The fast write mode is recommended for VCC > 2.5 V. http://onsemi.com 3 CAT25AM02 Pin Description Functional Description SI: The serial data input pin accepts op−codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. SO: The serial data output pin is used to transfer data out of the device. In SPI modes (0,0) and (1,1) data is shifted out on the falling edge of the SCK clock. SCK: The serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and CAT25AM02. CS: The chip select input pin is used to enable/disable the CAT25AM02. When CS is high, the SO output is tri−stated (high impedance) and the device is in Standby Mode (unless an internal write operation is in progress). Every communication session between host and CAT25AM02 must be preceded by a high to low transition and concluded with a low to high transition of the CS input. WP: The write protect input pin will allow all write operations to the device when held high. When WP pin is tied low and the WPEN bit in the Status Register (refer to Status Register description, later in this Data Sheet) is set to “1”, writing to the Status Register is disabled. HOLD: The HOLD input pin is used to pause transmission between host and CAT25AM02, without having to retransmit the entire sequence at a later time. To pause, HOLD must be taken low and to resume it must be taken back high, with the SCK input low during both transitions. The CAT25AM02 device supports the Serial Peripheral Interface (SPI) bus protocol, modes (0,0) and (1,1). The device contains an 8−bit instruction register. The instruction set and associated op−codes are listed in Table 7. Reading data stored in the CAT25AM02 is accomplished by simply providing the READ command and an address. Writing to the CAT25AM02, in addition to a WRITE command, address and data, also requires enabling the device for writing by first setting certain bits in a Status Register, as will be explained later. After a high to low transition on the CS input pin, the CAT25AM02 will accept any one of the six instruction op−codes listed in Table 7 and will ignore all other possible 8−bit combinations. The communication protocol follows the timing from Figure 2. The CAT25AM02 features an additional Identification Page (256 bytes) which can be accessed for Read and Write operations when the IPL bit from the Status Register is set to “1”. The user can also choose to make the Identification Page permanent write protected by setting the LIP bit from the Status Register (LIP=“1”). Table 7. INSTRUCTION SET Instruction Opcode WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 0011 Read Data from Memory WRITE 0000 0010 Write Data to Memory Figure 2. Synchronous Data Timing http://onsemi.com 4 Operation CAT25AM02 Status Register The WPEN (Write Protect Enable) bit acts as an enable for the WP pin. Hardware write protection is enabled when the WP pin is low and the WPEN bit is 1. This condition prevents writing to the status register and to the block protected sections of memory. While hardware write protection is active, only the non−block protected memory can be written. Hardware write protection is disabled when the WP pin is high or the WPEN bit is 0. The WPEN bit, WP pin and WEL bit combine to either permit or inhibit Write operations, as detailed in Table 10. The IPL (Identification Page Latch) bit determines whether the additional Identification Page (IPL = 1) or main memory array (IPL = 0) can be accessed both for Read and Write operations. The IPL bit is set by the user with the WRSR command and is volatile. The IPL bit is automatically reset after read/write operations. The LIP bit is set by the user with the WRSR command and is non-volatile. When set to 1, the Identification Page is permanently write protected (locked in Read-only mode). Note: The IPL and LIP bits cannot be set to 1 using the same WRSR instruction. If the user attempts to set (“1”) both the IPL and LIP bit in the same time, these bits cannot be written and therefore they will remain unchanged. The Status Register, as shown in Table 8, contains a number of status and control bits. The RDY (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. For the host, this bit is read only. The WEL (Write Enable Latch) bit is set/reset by the WREN/WRDI commands. When set to 1, the device is in a Write Enable state and when set to 0, the device is in a Write Disable state. The BP0 and BP1 (Block Protect) bits determine which blocks are currently write protected. They are set by the user with the WRSR command and are non−volatile. The user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to Table 9. The protected blocks then become read−only. The TWC (Write Cycle Time) bit is set by the user with the WRSR command and is volatile. When set to 0, the device is in a standard write mode with optimum ICC write, when set to 1 the device is in a fast write mode. Note: The fast write mode is recommended to be used only with VCC > 2.5 V. Table 8. STATUS REGISTER 7 6 5 4 3 2 1 0 WPEN IPL TWC LIP BP1 BP0 WEL RDY Table 9. BLOCK PROTECTION BITS Status Register Bits BP1 BP0 0 0 None No Protection 0 1 30000h−3FFFFh Quarter Array Protection 1 0 20000h−3FFFFh Half Array Protection 1 1 00000h−3FFFFh Full Array Protection Array Address Protected Protection Table 10. WRITE PROTECT CONDITIONS WPEN WP WEL Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable http://onsemi.com 5 CAT25AM02 Write Operations Write Enable and Write Disable The CAT25AM02 device powers up into a write disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the memory array or to the status register. In addition, the address of the memory location(s) to be written must be outside the protected area, as defined by BP0 and BP1 bits from the status register. The internal Write Enable Latch and the corresponding Status Register WEL bit are set by sending the WREN instruction to the CAT25AM02. Care must be taken to take the CS input high after the WREN instruction, as otherwise the Write Enable Latch will not be properly set. WREN timing is illustrated in Figure 3. The WREN instruction must be sent prior any WRITE or WRSR instruction. The internal write enable latch is reset by sending the WRDI instruction as shown in Figure 4. Disabling write operations by resetting the WEL bit, will protect the device against inadvertent writes. CS SCK SI 0 0 0 0 0 1 1 0 HIGH IMPEDANCE SO Note: Dashed Line = mode (1, 1) Figure 3. WREN Timing CS SCK SI SO 0 0 0 0 0 1 0 HIGH IMPEDANCE Note: Dashed Line = mode (1, 1) Figure 4. WRDI Timing http://onsemi.com 6 0 CAT25AM02 Byte Write Following completion of the write cycle, the CAT25AM02 is automatically returned to the write disable state. Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 24−bit address and a data byte as shown in Figure 5. Only 18 significant address bits are used by the CAT25AM02. The rest are don’t care bits, as shown in Table 11. Internal programming will start after the low to high CS transition. During an internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored. The RDY bit will indicate if the internal write cycle is in progress (RDY high), or the device is ready to accept commands (RDY low). Write Identification Page The additional 256-byte Identification Page (IP) can be written with user data using the same Write commands sequence as used for Page Write to the main memory array (Figure 6). The IPL bit from the Status Register must be set (IPL = 1) using the WRSR instruction, before attempting to write to the IP. Prior to any write to the Identification Page, the Write Enable Latch must be set (WEL=1) by sending the WREN instruction. The address bits [A23:A8] are Don’t Care and the [A7:A0] bits define the byte address within the Identification Page. In addition, the Byte Address must point to a location outside the protected area defined by the BP1, BP0 bits from the Status Register. When the full memory array is write protected (BP1, BP0 = 1,1), the write instruction to the IP is not accepted and not executed. Also, the write to the IP is not accepted if the LIP bit from the Status Register is set to 1 (the page is locked in Read-only mode). Page Write After sending the first data byte to the CAT25AM02, the host may continue sending data, up to a total of 256 bytes, according to timing shown in Figure 6. After each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. If during this process the end of page is exceeded, then loading will “roll over” to the first byte in the page, thus possibly overwriting previoualy loaded data. Table 11. BYTE ADDRESS Address Significant Bits Address Don’t Care Bits # Address Clock Pulses Main Memory Array Device A17 − A0 A23 – A18 24 Identification Page A7 − A0 A23 – A8 24 CS 0 1 2 3 4 5 6 7 8 29 30 31 32 33 34 35 36 37 38 39 SCK OPCODE SI 0 0 0 0 0 0 BYTE ADDRESS* 1 AN 0 DATA IN A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE SO * Please check the Byte Address Table (Table 11) Note: Dashed Line = mode (1, 1) Figure 5. Byte WRITE Timing CS 0 1 2 3 4 5 6 7 8 29 30 31 32−39 40−47 32+(N−1)x8−1....32+(N−1)x8 32+Nx8−1 SCK BYTEADDRESS* OPCODE SI SO 0 0 0 0 0 0 1 0 DATA IN Data Data A0 Byte 1 Byte 2 AN Data Byte N 0 7..1 HIGH IMPEDANCE * Please check the Byte Address Table (Table 11) Note: Dashed Line = mode (1, 1) Figure 6. Page WRITE Timing http://onsemi.com 7 CAT25AM02 Write Status Register Write Protection The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2, 3, 4, 5, 6 and 7 can be written using the WRSR command. The Write Protect (WP) pin can be used to protect the Block Protect bits BP0 and BP1 against being inadvertently altered. When WP is low and the WPEN bit is set to “1”, write operations to the Status Register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the Status Register. The WP pin function is blocked when the WPEN bit is set to “0”. The WP input timing is shown in Figure 8. CS 0 1 2 3 4 5 6 7 8 9 10 11 1 7 6 5 4 12 13 14 15 2 1 0 SCK OPCODE 0 SI 0 0 0 0 DATA IN 0 0 MSB HIGH IMPEDANCE SO Note: Dashed Line = mode (1, 1) Figure 7. WRSR Timing tWPS tWPH CS SCK WP WP Note: Dashed Line = mode (1, 1) Figure 8. WP Timing http://onsemi.com 8 3 CAT25AM02 Read Operations Read Identification Page Reading the additional 256-byte Identification Page (IP) is achieved using the same Read command sequence as used for Read from main memory array (Figure 10). The IPL bit from the Status Register must be set (IPL = 1) before attempting to read from the IP. The [A7:A0] are the address significant bits that point to the data byte shifted out on the SO pin. If the CS continues to be held low, the internal address register defined by [A7:A0] bits is automatically incremented and the next data byte from the IP is shifted out. The byte address must not exceed the 256-byte page boundary. Read from Memory Array To read from memory, the host sends a READ instruction followed by a 24−bit address (see Table 11 for the number of significant address bits). After receiving the last address bit, the CAT25AM02 will respond by shifting out data on the SO pin (as shown in Figure 9). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter “rolls over” to the lowest memory address, and the read cycle can be continued indefinitely. The read operation is terminated by taking CS high. Read Status Register To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAT25AM02 will shift out the contents of the status register on the SO pin (Figure 10). The status register may be read at any time, including during an internal write cycle. CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCK OPCODE SI 0 0 0 0 0 BYTE ADDRESS* 0 1 1 A0 AN DATA OUT HIGH IMPEDANCE SO 7 6 5 4 3 2 1 0 MSB * Please check the Byte Address Table (Table 11) Note: Dashed Line = mode (1, 1) Figure 9. READ Timing CS 0 1 2 3 4 5 6 7 1 0 1 8 9 10 11 7 6 5 4 12 13 14 2 1 SCK OPCODE SI SO 0 0 0 0 0 DATA OUT HIGH IMPEDANCE MSB Note: Dashed Line = mode (1, 1) Figure 10. RDSR Timing http://onsemi.com 9 3 0 CAT25AM02 Hold Operation below the POR trigger level. This bi−directional POR behavior protects the device against ‘brown−out’ failure following a temporary loss of power. The CAT25AM02 device powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued prior any writes to the device. After power up, the CS pin must be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the device goes into a write disable mode. The CS input must be set high after the proper number of clock cycles to start the internal write cycle. Access to the memory array during an internal write cycle is ignored and programming is continued. Any invalid op−code will be ignored and the serial output pin (SO) will remain in the high impedance state. The HOLD input can be used to pause communication between host and CAT25AM02. To pause, HOLD must be taken low while SCK is low (Figure 11). During the hold condition the device must remain selected (CS low). During the pause, the data output pin (SO) is tri−stated (high impedance) and SI transitions are ignored. To resume communication, HOLD must be taken high while SCK is low. Design Considerations The CAT25AM02 device incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops CS tCD tCD SCK tHD tHD HOLD tHZ SO HIGH IMPEDANCE tLZ Note: Dashed Line = mode (1, 1) Figure 11. HOLD Timing http://onsemi.com 10 CAT25AM02 PACKAGE DIMENSIONS ÈÈ ÈÈ E PIN A1 REFERENCE WLCSP8, 3.12x2.04 CASE 567GV ISSUE A A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. DIMENSION b IS MEASURED AT THE MAXIMUM BALL DIAMETER PARALLEL TO DATUM C. A3 A2 DIE COAT (OPTIONAL) D DIM A A1 A2 A3 b D E e e1 e2 e3 2X DETAIL A 0.10 C 2X 0.10 C TOP VIEW DETAIL A A 0.10 C 0.08 C A1 NOTE 3 SIDE VIEW C SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* e 8X 0.05 C A 0.03 C NOTE 3 PIN A1 REFERENCE 0.700 PACKAGE OUTLINE e1 b B D 1.100 C e2 2.100 e3 B 8X 0.125 A 1 2 e1/2 MILLIMETERS MIN MAX −−− 0.37 0.06 0.10 0.23 REF 0.025 REF 0.11 0.14 3.12 BSC 2.04 BSC 1.40 BSC 1.00 BSC 1.10 BSC 2.10 BSC 3 4 e/2 BOTTOM VIEW 1.000 1.400 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 11 CAT25AM02 DIE SIZE AND PAD LOCATION Pad Location* 2030 μm CS SO Pad Pad Name X Y Unit 1 CS -878.14 1482.5 m VCC 2 SO -918.14 1314.5 m HOLD 3 WP -918.14 -1342.5 m 4 GND -878.14 -1482.5 m 5 SI 888.14 -1467.5 m 6 SCK 928.14 -1327.5 m 7 HOLD 943.14 1342.5 m 8 VDD 903.14 1482.5 m 3107 μm * Pads location coordinates relative to the origin at the center of the die. Die−Pad Configuration Diagram SCK WP Die ID VSS SI NOTCH EDGE OF THE WAFER Die Mechanical Dimensions Specification Bond pad opening Min Typ - Bond pad spacing 136 5.354 Die thickness 200 8 - Max Unit 70 x 70 2.755 x 2.755 - m mils 140 5.511 - m mils - 660.4 26 m mils 12.7 0.5 m mils m mils Die size before saw-cut (wafer stepping) - 2080 x 3157 81.889 x 124.291 25.4 1 - Die size after saw-cut - 2030 x 3107 81.889 x 124.291 - Die thickness tolerance http://onsemi.com 12 m mils CAT25AM02 ORDERING INFORMATION Device Order Number Specific Device Marking Package Type Lead Finish CAT25AM02DTR (Notes 12, 13, 14) − Die in Tape & Reel CAT25AM02DWF (Notes 13, 14) − Wafer Unsawn CAT25AM02C8ATR (Note 14) EA2M WLCSP−8 SnAg Tape & Reel, 2,000 Units / Reel CAT25AM02C8CTR (Note 14) EA2M WLCSP−8 with Die Coat SnAg Tape & Reel, 2,000 Units / Reel Shipping Tape & Reel, 3,000 Units / Reel 11. All packages are RoHS−compliant (Lead−free, Halogen−free). 12. CAT25AM02DTR: Die in Tape & Reel with die thickness = 8 mil ± 0.5 mil 13. For Die Sales additional information, please contact factory. 14. Caution: The EEPROM devices delivered in bare die form or WLCSP must never be exposed to ultra violet light! When exposed to ultra violet light the EEPROM cells lose their stored data. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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