CAT25C256LI-G

CAT25C128/256 CAT25C128/256 128K/256K-Bit SPI Serial CMOS EEPROM FEATURES ■ Self-Timed Write Cycle ■ 5 MHz SPI Compatible ■ 64-Byte Page Write Buffer ■ 1.8 to 5.5 Volt Operation ■ Block Write Protection ■ Hardware and Software Protection – Protect 1/4, 1/2 or all of EEPROM Array ■ Low Power CMOS Technology ■ 100,000 Program/Erase Cycles ■ SPI Modes (0,0 &1,1) ■ 100 Year Data Retention ■ Industrial and Automotive ■ RoHS-compliant packages Temperature Ranges DESCRIPTION The CAT25C128/256 is a 128K/256K-Bit SPI Serial CMOS EEPROM internally organized as 16Kx8/32Kx8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C128/256 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled through a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C128/256 is designed with software and hardware write protection features including Block Lock protection. The device is available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and 20-pin TSSOP packages. PIN CONFIGURATION CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI CS SO NC NC NC WP VSS SS 14 13 12 11 5 10 6 9 7 8 V CC HOLD NC NC NC SCK SI SENSE AMPS SHIFT REGISTERS WORD ADDRESS BUFFERS VCC HOLD SCK SI **CAT25C128 only. NC CS SO SO NC NC WP VSS NC NC 1 2 20 19 3 4 18 17 5 16 6 15 14 13 12 11 7 8 9 10 SO SI NC V CC HOLD HOLD NC NC SCK SI NC NC CS WP HOLD SCK I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC Function Serial data Output Serial Clock Write Protect Power Supply Ground Chip Select Serial Data Input Suspends Serial Input No Connect © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice. XDEC COLUMN DECODERS EE PROM ARRAY DATA IN STORAGE PIN FUNCTIONS Pin Name SO SCK WP VCC VSS CS SI HOLD NC CONTROL LOGIC CS SO WP 8 7 6 5 1 2 3 4 TSSOP Package (Y20)** DIP Package (L) 1 2 3 4 BLOCK DIAGRAM TSSOP Package (Y14)** SOIC Package (V**, X) HIGH VOLTAGE/ TIMING CONTROL STATUS REGISTER For Ordering Information details, see page 11. 1 Document No. MD-1018, Rev. J CAT25C128/256 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS1) ................... –2.0V to +VCC +2.0V VCC with Respect to VSS ................................ –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (3) Parameter Min. Endurance Max. Units 100,000 Cycles/Byte TDR(3) Data Retention 100 Years VZAP(3) ESD Susceptibility 2000 Volts ILTH(3)(4) Latch-Up 100 mA D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC1 Power Supply Current (Operating Write) 10 mA VCC = 5V @ 5MHz SO=open; CS=Vss ICC2 Power Supply Current (Operating Read) 2 mA VCC = 5.0V FCLK = 5MHz ISB(5) Power Supply Current (Standby) 1 µA CS = VCC VIN = VSS or VCC ILI Input Leakage Current 2 µA ILO Output Leakage Current 3 µA VIL(3) Input Low Voltage -1 VCC x 0.3 V VIH(3) Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage 0.4 V VOH1 Output High Voltage VOL2 Output Low Voltage VOH2 Output High Voltage VCC - 0.8 V 0.2 VCC-0.2 VOUT = 0V to VCC, CS = 0V 4.5V≤VCC