CAT28C16AW-12T

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Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others. CAT28C16A 16 kb CMOS Parallel EEPROM Description The CAT28C16A is a fast, low power, 5V−only CMOS Parallel EEPROM organized as 2K x 8−bits. It requires a simple interface for in−system programming. On−chip address and data latches, self−timed write cycle with auto−clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling signals the start and end of the self−timed write cycle. Additionally, the CAT28C16A features hardware write protection. The CAT28C16A is manufactured using ON Semiconductor’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 24−pin DIP and SOIC or 32−pin PLCC packages. http://onsemi.com SOIC−24 J, K, W, X SUFFIX CASE 751BK Features • Fast Read Access Times: 90 ns, 120 ns, 200 ns • Low Power CMOS Dissipation: • • • • • • • • PDIP−24 L SUFFIX CASE 646AD – Active: 25 mA Max. – Standby: 100 mA Max. Simple Write Operation: – On−chip Address and Data Latches – Self−timed Write Cycle with Auto−clear Fast Write Cycle Time: 10 ms Max End of Write Detection: DATA Polling Hardware Write Protection CMOS and TTL Compatible I/O 100,000 Program/Erase Cycles 100 Year Data Retention Commercial, Industrial and Automotive Temperature Ranges PIN FUNCTION Pin Name A0−A10 I/O0−I/O7 PIN CONFIGURATION DIP Package (L) SOIC Package (J, K, W, X) 24 23 3 22 4 21 5 6 20 19 7 8 18 17 9 16 10 11 15 14 12 13 A7 NC NC NC VCC WE NC 1 2 PLCC Package (N, G) VCC A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A6 A5 A4 A3 A2 A1 A0 NC I/O0 © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 6 Function Address Inputs Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable VCC 5 V Supply VSS Ground NC No Connect ORDERING INFORMATION 4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 25 TOP VIEW 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 A8 A9 NC NC OE A10 CE I/O7 I/O6 See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS PLCC−32 N, G SUFFIX CASE 776AK 1 Publication Order Number: CAT28C16A/D CAT28C16A VCC INADVERTENT WRITE PROTECTION CE OE WE CONTROL LOGIC 2,048 x 8 EEPROM ARRAY ROW DECODER ADDR. BUFFER & LATCHES A4−A10 HIGH VOLTAGE GENERATOR I/O BUFFERS TIMER DATA POLLING I/O0−I/O7 ADDR. BUFFER & LATCHES A0−A3 COLUMN DECODER Figure 1. Block Diagram Table 1. MODE SELECTION Mode CE WE Read L H Byte Write (WE Controlled) L Byte Write (CE Controlled) OE I/O Power L DOUT ACTIVE H DIN ACTIVE L H DIN ACTIVE Standby, and Write Inhibit H X X High−Z STANDBY Read and Write Inhibit X H H High−Z ACTIVE Max Conditions Units Table 2. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5 V) Symbol Test CI/O (Note 1) Input/Output Capacitance 10 VI/O = 0 V pF CIN (Note 1) Input Capacitance 6 VIN = 0 V pF 1. This parameter is tested initially and after a design or process change that affects the parameter. Table 3. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Temperature Under Bias –55 to +125 °C Storage Temperature –65 to +150 °C –2.0 V to +VCC + 2.0 V V −2.0 to +7.0 V Package Power Dissipation Capability (TA = 25°C) 1.0 W Lead Soldering Temperature (10 secs) 300 °C Output Short Circuit Current (Note 3) 100 mA Voltage on Any Pin with Respect to Ground (Note 2) VCC with Respect to Ground Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. http://onsemi.com 2 CAT28C16A Table 4. RELIABILITY CHARACTERISTICS (Note 4) Symbol Parameter NEND (Note 5) Endurance TDR (Notes 5) Data Retention VZAP ILTH (Note 6) Min ESD Susceptibility Latch−Up Max Units 100,000 Cycles/Byte 100 Years 2,000 V 100 mA 4. This parameter is tested initially and after a design or process change that affects the parameter. 5. For the CAT28C16A−20, the minimum endurance is 10,000 cycles and the minimum data retention is 10 years. 6. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V. Table 5. D.C. OPERATING CHARACTERISTICS (VCC = 5 V ±10%, unless otherwise specified.) Limits Symbol ICC Parameter Min Test Conditions Typ Max Units VCC Current (Operating, TTL) CE = OE = VIL, f = 1/tRC min, All I/O’s Open 35 mA VCC Current (Operating, CMOS) CE = OE = VILC, f = 1/tRC min, All I/O’s Open 25 mA VCC Current (Standby, TTL) CE = VIH, All I/O’s Open 1 mA VCC Current (Standby, CMOS) CE = VIHC, All I/O’s Open 100 mA ILI Input Leakage Current VIN = GND to VCC −10 10 mA ILO Output Leakage Current VOUT = GND to VCC, CE = VIH −10 10 mA VIH (Note 8) High Level Input Voltage 2 VCC + 0.3 V VIL (Note 7) Low Level Input Voltage −0.3 0.8 V ICCC (Note 7) ISB ISBC (Note 8) VOH High Level Output Voltage IOH = −400 mA VOL Low Level Output Voltage IOL = 2.1 mA VWI Write Inhibit Voltage 2.4 V 0.4 3.0 V V 7. VILC = −0.3 V to +0.3 V 8. VIHC = VCC − 0.3 V to VCC + 0.3 V Table 6. A.C. CHARACTERISTICS, READ CYCLE (VCC = 5 V ±10%, unless otherwise specified.) 28C16A−90 Symbol Parameter Min Max 90 28C16A−12 Min Max Min Max Read Cycle Time tCE CE Access Time 90 120 200 ns tAA Address Access Time 90 120 200 ns tOE OE Access Time 50 60 80 ns CE Low to Active Output 0 tOLZ (Note 9) OE Low to Active Output 0 200 Units tRC tLZ (Note 9) 120 28C16A−20 0 ns 0 0 ns 0 ns tHZ (Notes 9, 10) CE High to High−Z Output 50 50 55 ns tOHZ (Notes 9, 10) OE High to High−Z Output 50 50 55 ns tOH (Note 9) Output Hold from Address Change 0 0 0 9. This parameter is tested initially and after a design or process change that affects the parameter. 10. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer. http://onsemi.com 3 ns CAT28C16A 2.4 V 2.0 V INPUT PULSE LEVELS REFERENCE POINTS 0.8 V 0.45 V Figure 2. A.C. Testing Input/Output Waveform (Note 11) 11. Input rise and fall times (10% and 90%) < 10 ns. 1.3V 1N914 3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE Figure 3. A.C. Testing Load Circuit (example) Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 5 V ±10%, unless otherwise specified.) 28C16A−90 Parameter Symbol Min Max 28C16A−12 Min Max 5 28C16A−20 Min 5 Max Units 10 ms tWC Write Cycle Time tAS Address Setup Time 0 0 10 ns tAH Address Hold Time 100 100 100 ns tCS CE Setup Time 0 0 0 ns tCH CE Hold Time 0 0 0 ns tCW (Note 12) CE Pulse Time 110 110 150 ns tOES OE Setup Time 0 0 15 ns tOEH OE Hold Time 0 0 15 ns tWP (Note 12) WE Pulse Width 110 110 150 ns tDS Data Setup Time 60 60 50 ns tDH Data Hold Time 0 0 10 ns tDL Data Latch Time 5 10 5 10 50 ns 0.05 100 0.05 100 5 tINIT (Note 13) Write Inhibit Period After Power−up 12. A write pulse of less than 20 ns duration will not initiate a write cycle. 13. This parameter is tested initially and after a design or process change that affects the parameter. http://onsemi.com 4 20 ms CAT28C16A DEVICE OPERATION Read Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2−line control architecture can be used to eliminate bus contention in a system environment. tRC ADDRESS tCE CE tOE OE WE tOLZ VIH tLZ tHZ tOH HIGH−Z DATA OUT tOHZ tAA DATA VALID DATA VALID Figure 4. Read Cycle tWC ADDRESS tAS tAH tCH tCS CE OE tOES tOEH tWP WE tDL DATA OUT DATA IN HIGH−Z DATA VALID tDS tDH Figure 5. Byte Write Cycle [WE Controlled] Byte Write edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling http://onsemi.com 5 CAT28C16A DATA Polling complement of that data on I/O7 (I/O0–I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self−timed byte write cycle, all I/O’s will output true data during a read cycle. DATA polling is provided to indicate the completion of a byte write cycle. Once a byte write cycle is initiated, attempting to read the last byte written will output the tWC ADDRESS tAS tAH tDL tCW CE tOEH OE tCS tOES tCH WE HIGH−Z DATA OUT DATA IN DATA VALID tDS tDH Figure 6. Byte Write Cycle [CE Controlled] ADDRESS CE WE tOEH tOES tOE OE tWC I/O7 DOUT = X DIN = X DOUT = X Figure 7. DATA Polling Hardware Data Protection The following is a list of hardware data protection features that are incorporated into the CAT28C16A. 1. VCC sense provides for write protection when VCC falls below 3.0 V min. 2. A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 20 ms delay before a write sequence, after VCC has reached 3.0 V min. 3. Write inhibit is activated by holding any one of OE low, CE high or WE high. 4. Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. http://onsemi.com 6 CAT28C16A PACKAGE DIMENSIONS PLCC 32 CASE 776AK−01 ISSUE O PIN#1 IDENTIFICATION E1 E E2 D1 A2 D A3 TOP VIEW END VIEW b1 b e D2 SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-016. SYMBOL MIN A2 0.38 A3 2.54 2.80 7 MAX b 0.33 0.54 b1 0.66 0.82 D 12.32 12.57 D1 11.36 11.50 D2 9.56 11.32 E 14.86 15.11 E1 13.90 14.04 E2 12.10 13.86 e http://onsemi.com NOM 1.27 BSC CAT28C16A PACKAGE DIMENSIONS SOIC−24, 300 mils CASE 751BK−01 ISSUE O E1 SYMBOL MIN A 2.35 2.65 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.51 c 0.20 0.33 D 15.20 15.40 E 10.11 10.51 E1 7.34 7.60 E e b e PIN#1 IDENTIFICATION NOM MAX 1.27 BSC h 0.25 0.75 L 0.40 1.27 θ 0º 8º θ1 5º 15º TOP VIEW h D A2 A A1 SIDE VIEW h q1 q q1 L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. http://onsemi.com 8 c CAT28C16A PACKAGE DIMENSIONS PDIP−24, 600 mils CASE 646AD−01 ISSUE A SYMBOL MIN NOM A E1 E D 6.35 A1 0.39 A2 3.18 4.95 b 0.36 0.55 b1 0.77 1.77 c 0.21 0.38 D 31.50 32.25 E 15.24 15.87 E1 12.32 e TOP VIEW A2 14.73 2.54 BSC eB 15.24 17.78 L 2.93 5.08 A c A1 b1 e L b eB SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-011. http://onsemi.com 9 MAX CAT28C16A Example of Ordering Information Prefix Device # Suffix CAT 28C16A N Company ID (Optional) Product Number 28C16A I − 20 T Temperature Range Speed Tape & Reel (Note 15) T: Tape & Reel Blank = Commercial (0°C to +70°C) I = Industrial (−40°C to +85°C) A = Automotive (−40°C to +105°C) −90: 90 ns −12: 120 ns −20: 200 ns Package N: PLCC J: SOIC (JEDEC) K: SOIC (EIAJ) L: PDIP (Lead Free, Halogen Free) G: PLCC (Lead Free, Halogen Free) W: SOIC (JEDEC) (Lead Free, Halogen Free) X: SOIC (EIAJ) (Lead Free, Halogen Free) 14. The device used in the above example is a CAT28C16ANI−20T (PLCC, Industrial Temperature, 200 ns Access Time, Tape & Reel). 15. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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