CAT28LV65XI-25T

CAT28LV65 64 kb CMOS Parallel EEPROM Description The CAT28LV65 is a low voltage, low power, CMOS Parallel EEPROM organized as 8K x 8−bits. It requires a simple interface for in −system programming. On −chip address and data latches, self−timed write cycle with auto−clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling, RDY/BUSY and Toggle status bit signal the start and end of the self−timed write cycle. Additionally, the CAT28LV65 features hardware and software write protection. The CAT28LV65 is manufactured using ON Semiconductor’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28−pin DIP, 28−pin TSOP, 28−pin SOIC or 32−pin PLCC packages. Features http://onsemi.com PDIP−28 P, L SUFFIX CASE 646AE SOIC−28 J, K, W, X SUFFIX CASE 751BM • 3.0 V to 3.6 V Supply • Read Access Times: • • • • • • • • • • • – 150/200/250 ns Low Power CMOS Dissipation: – Active: 8 mA Max. – Standby: 100 mA Max. Simple Write Operation: – On−chip Address and Data Latches – Self−timed Write Cycle with Auto−clear Fast Write Cycle Time: – 5 ms Max. Commercial, Industrial and Automotive Temperature Ranges CMOS and TTL Compatible I/O Automatic Page Write Operation: – 1 to 32 bytes in 5 ms – Page Load Timer End of Write Detection: – Toggle Bit – DATA Polling – RDY/BUSY Hardware and Software Write Protection 100,000 Program/Erase Cycles 100 Year Data Retention These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant PLCC−32 N, G SUFFIX CASE 776AK TSOP−28 H13 SUFFIX CASE 318AE PIN FUNCTION Pin Name A0−A12 I/O0−I/O7 CE OE RDY/BSY WE VCC VSS NC Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Ready/BUSY Status Write Enable 3.0 V to 3.6 V Supply Ground No Connect ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 7 1 Publication Order Number: CAT28LV65/D CAT28LV65 PIN CONFIGURATIONS DIP Package (P, L) RDY/BUSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 SOIC Package (J, K, W, X) RDY/BUSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PLCC Package (N, G) A7 A12 RDY/BUSY NC VCC WE NC TSOP Package (8 mm x 13.4 mm) (H13) OE A11 A9 A8 NC WE VCC RDY/BUSY A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A6 A5 A4 A3 A2 A1 A0 NC I/O0 4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 A8 A9 A11 NC OE A10 CE I/O7 I/O6 (Top Views) http://onsemi.com 2 CAT28LV65 A5−A12 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 8,192 x 8 E2PROM ARRAY 32 BYTE PAGE REGISTER VCC HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC DATA POLLING RDY/BUSY & TOGGLE BIT COLUMN DECODER I/O BUFFERS TIMER ADDR. BUFFER & LATCHES I/O0−I/O7 A0−A4 RDY/BUSY Figure 1. Block Diagram Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground (Note 1) VCC with Respect to Ground Package Power Dissipation Capability (TA = 25°C) Lead Soldering Temperature (10 secs) Output Short Circuit Current (Note 2) Ratings –55 to +125 –65 to +150 –2.0 V to +VCC + 2.0 V −2.0 to +7.0 1.0 300 100 Units °C °C V V W °C mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time. Table 2. RELIABILITY CHARACTERISTICS (Note 3) Symbol NEND TDR VZAP ILTH (Note 4) Parameter Endurance Data Retention ESD Susceptibility Latch−Up Test Method MIL−STD−883, Test Method 1033 MIL−STD−883, Test Method 1008 MIL−STD−883, Test Method 3015 JEDEC Standard 17 Min 105 100 2,000 100 Max Units Cycles/Byte Years V mA 3. These parameters are tested initially and after a design or process change that affects the parameters. 4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V. Table 3. MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High−Z High−Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE http://onsemi.com 3 CAT28LV65 Table 4. CAPACITANCE (TA = 25°C, f = 1.0 MHz) Symbol CI/O (Note 5) CIN (Note 5) Test Input/Output Capacitance Input Capacitance Max 10 6 Conditions VI/O = 0 V VIN = 0 V Units pF pF 5. This parameter is tested initially and after a design or process change that affects the parameter. Table 5. D.C. OPERATING CHARACTERISTICS (VCC = 3.0 V to 3.6 V, unless otherwise specified.) Limits Symbol ICC ISBC (Note 6) ILI ILO VIH (Note 6) VIL VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage IOH = −100 mA IOL = 1.0 mA 2 Test Conditions CE = OE = VIL, f = 1/tRC min, All I/O’s Open CE = VIHC, All I/O’s Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH −1 −5 2 −0.3 2 0.3 Min Typ Max 8 100 1 5 VCC + 0.3 0.6 Units mA mA mA mA V V V V V 6. VIHC = VCC − 0.3 V to VCC + 0.3 V. Table 6. A.C. CHARACTERISTICS, READ CYCLE (VCC = 3.0 V to 3.6 V, unless otherwise specified.) 28LV65−15 Symbol tRC tCE tAA tOE tLZ (Note 7) tOLZ (Note 7) tHZ (Notes 7, 8) tOHZ (Notes 7, 8) tOH (Note 7) Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time CE Low to Active Output OE Low to Active Output CE High to High−Z Output OE High to High−Z Output Output Hold from Address Change 0 0 0 50 50 0 Min 150 150 150 70 0 0 50 50 0 Max 28LV65−20 Min 200 200 200 80 0 0 55 55 Max 28LV65−25 Min 250 250 250 100 Max Units ns ns ns ns ns ns ns ns ns 7. This parameter is tested initially and after a design or process change that affects the parameter. 8. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer. http://onsemi.com 4 CAT28LV65 VCC − 0.3 V INPUT PULSE LEVELS 0.0 V 2.0 V 0.6 V REFERENCE POINTS Figure 2. A.C. Testing Input/Output Waveform (Note 9) 9. Input rise and fall times (10% and 90%) < 10 ns. VCC 1.8 K DEVICE UNDER TEST 1. 3 K CL = 100 pF OUTPUT CL INCLUDES JIG CAPACITANCE Figure 3. A.C. Testing Load Circuit (example) Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 3.0 V to 3.6 V, unless otherwise specified.) 28LV65−15 Symbol tWC tAS tAH tCS tCH tCW (Note 10) tOES tOEH tWP (Note 10) tDS tDH tINIT (Note 11) tBLC (Notes 11, 12) tRB Parameter Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time CE Pulse Time OE Setup Time OE Hold Time WE Pulse Width Data Setup Time Data Hold Time Write Inhibit Period After Power−up Byte Load Cycle Time WE Low to RDY/BUSY Low 0 100 0 0 110 0 0 110 60 0 5 0.05 10 100 220 Min Max 5 0 100 0 0 150 10 10 150 100 0 5 0.1 10 100 220 28LV65−20 Min Max 5 0 100 0 0 150 10 10 150 100 0 5 0.1 10 100 220 28LV65−25 Min Max 5 Units ms ns ns ns ns ns ns ns ns ns ns ms ms ns 10. A write pulse of less than 20 ns duration will not initiate a write cycle. 11. This parameter is tested initially and after a design or process change that affects the parameter. 12. A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. http://onsemi.com 5 CAT28LV65 DEVICE OPERATION Read Byte Write Data stored in the CAT28LV65 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2−line control architecture can be used to eliminate bus contention in a system environment. tRC ADDRESS tCE CE tOE OE VIH tLZ tOLZ A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. WE tAA tOH DATA VALID tOHZ tHZ DATA VALID DATA OUT HIGH−Z Figure 4. Read Cycle tWC ADDRESS tAS CE tCS tAH tCH OE tOES WE tRB HIGH−Z RDY/BUSY HIGH−Z tBLC HIGH−Z tWP tOEH DATA OUT DATA IN DATA VALID tDS tDH Figure 5. Byte Write Cycle [WE Controlled] http://onsemi.com 6 CAT28LV65 Page Write The page write mode of the CAT28LV65 (essentially an extended BYTE WRITE mode) allows from 1 to 32 bytes of data to be programmed within a single EEPROM write cycle. This effectively reduces the byte−write time by a factor of 32. Following an initial WRITE operation (WE pulsed low, for tWP, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 32 byte temporary buffer. The page address where data is to be written, specified by bits A5 to A12, is latched on the last falling edge of WE. Each byte within the page is defined by address bits A0 to A4 (which can be loaded ADDRESS tAS CE tAH tCW in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tBLC MAX of the rising edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within tBLC MAX. Upon completion of the page write sequence, WE must stay high a minimum of tBLC MAX for the internal automatic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page. tWC tBLC tOEH OE tCS WE tRB HIGH−Z RDY/BUSY DATA OUT HIGH−Z HIGH−Z tOES tCH DATA IN DATA VALID tDS tDH Figure 6. Byte Write Cycle [CE Controlled] OE CE tWP WE tBLC ADDRESS tWC I/O BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 LAST BYTE BYTE n+2 Figure 7. Page Mode Write Cycle http://onsemi.com 7 CAT28LV65 DATA Polling DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0–I/O 6 are indeterminate) until the programming cycle is complete. Upon completion of the self−timed write cycle, all I/O’s will output true data during a read cycle. Toggle Bit write cycle. While a write cycle is in progress, reading data from the device will result in I/O6 toggling between one and zero. However, once the write is complete, I/O6 stops toggling and valid data can be read from the device. Ready/BUSY (RDY/BUSY) In addition to the DATA Polling feature, the device offers an additional method for determining the completion of a ADDRESS The RDY/BUSY pin is an open drain output which indicates device status during programming. It is pulled low during the write cycle and released at the end of programming. Several devices may be OR−tied to the same RDY/BUSY line. CE WE tOEH OE tWC I/O7 DIN = X DOUT = X DOUT = X tOE tOES Figure 8. DATA Polling WE CE tOEH OE tOE tOES I/O6 (Note 13) tWC (Note 13) Figure 9. Toggle Bit 13. Beginning and ending state of I/O6 is indeterminate. http://onsemi.com 8 CAT28LV65 Hardware Data Protection The following is a list of hardware data protection features that are incorporated into the CAT28LV65. 1. VCC sense provides for write protection when VCC falls below 2.0 V min. 2. A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 10 ms delay before a write sequence, after VCC has reached 2.40 V min. 3. Write inhibit is activated by holding any one of OE low, CE high or WE high. WRITE DATA: ADDRESS: AA 1555 4. Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. Software Data Protection The CAT28LV65 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from ON Semiconductor with the software protection NOT ENABLED (the CAT28LV65 is in the standard operating mode). WRITE DATA: ADDRESS: AA 1555 WRITE DATA: ADDRESS: 55 0AAA WRITE DATA: ADDRESS: 55 0AAA WRITE DATA: ADDRESS: A0 1555 WRITE DATA: ADDRESS: 80 1555 SOFTWARE DATA PROTECTION ACTIVATED (Note 14) WRITE DATA: ADDRESS: AA 1555 WRITE DATA: XX WRITE DATA: ADDRESS: 55 0AAA TO ANY ADDRESS WRITE LAST BYTE TO LAST ADDRESS WRITE DATA: ADDRESS: 20 1555 Figure 10. Write Sequence for Activating Software Data Protection Figure 11. Write Sequence for Deactivating Software Data Protection 14. Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max., after SDP activation. http://onsemi.com 9 CAT28LV65 Software Data Protection To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 10). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 12). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transitions. DATA ADDRESS CE AA 1555 55 0AAA This gives the user added inadvertent write protection on power−up in addition to the hardware protection provided. To allow the user the ability to program the device with an EEPROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 11) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 13 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. A0 1555 BYTE OR PAGE tWP tBLC WRITES ENABLED tWC WE Figure 12. Software Data Protection Timing DATA ADDRESS CE AA 1555 55 0AAA 80 1555 AA 1555 55 0AAA 20 1555 tWC SDP RESET DEVICE UNPROTECTED WE Figure 13. Resetting Software Data Protection Timing http://onsemi.com 10 CAT28LV65 PACKAGE DIMENSIONS PLCC 32 CASE 776AK−01 ISSUE O PIN#1 IDENTIFICATION E1 E E2 D1 D TOP VIEW A3 END VIEW A2 SYMBOL b1 A2 A3 b b1 b D2 SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-016. e D D1 D2 E E1 E2 e MIN 0.38 2.54 0.33 0.66 12.32 11.36 9.56 14.86 13.90 12.10 NOM MAX 2.80 0.54 0.82 12.57 11.50 11.32 15.11 14.04 13.86 1.27 BSC http://onsemi.com 11 CAT28LV65 PACKAGE DIMENSIONS SOIC−28, 300 mils CASE 751BM−01 ISSUE O SYMBOL A A1 A2 b E c D E E1 e h b PIN #1 IDENTIFICATION TOP VIEW e L 0.25 0.40 MIN 2.35 0.10 2.05 0.31 0.20 17.78 10.11 7.34 NOM MAX 2.65 0.30 2.55 0.51 0.33 18.03 10.51 7.60 1.27 BSC 0.75 1.27 θ θ1 0º 5º 8º 15º D h h q1 A2 A q A1 L E1 q1 c SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. END VIEW http://onsemi.com 12 CAT28LV65 PACKAGE DIMENSIONS PDIP−28, 600 mils CASE 646AE−01 ISSUE A SYMBOL A A1 A2 E1 E b b1 c D D E E1 e TOP VIEW eB L 15.24 2.93 0.39 3.18 0.36 0.77 0.21 35.10 15.24 12.32 2.54 BSC 17.78 5.08 4.95 0.55 1.77 0.38 39.70 15.87 14.73 MIN NOM MAX 6.35 A2 A c A1 b1 e b L eB SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-011. END VIEW http://onsemi.com 13 CAT28LV65 PACKAGE DIMENSIONS TSOP 28, 8x13.4 CASE 318AE−01 ISSUE O D1 A PIN 1 b E1 e D A1 A2 TOP VIEW q1 L2 END VIEW c SYMBOL A MIN 1.00 0.05 0.90 0.17 0.10 13.20 11.70 7.90 0.30 0.675 NOM 1.10 1.00 0.22 0.15 13.40 11.80 8.00 0.55 BSC 0.50 0.25 BSC MAX 1.20 0.15 1.05 0.27 0.20 13.60 11.90 8.10 0.70 q SIDE VIEW A1 L L1 A2 b c D D1 E e L L1 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-183. L2 θ θ1 0° 10° 3° 12° 5° 16° http://onsemi.com 14 CAT28LV65 Example of Ordering Information (Note 15) Prefix CAT Device # 28LV65 Suffix N I − 25 T Company ID (Optional) Product Number 28LV65 Temperature Range Blank = Commercial (0°C to +70°C) I = Industrial (−40°C to +85°C) A = Automotive (−40°C to +105°C) (Note 17) Speed Tape & Reel (Note 18) T: Tape & Reel Package P: PDIP (Note 16) J: SOIC (JEDEC) (Note 16) K: SOIC (EIAJ) (Note 16) N: PLCC (Note 16) L: PDIP (Lead Free, Halogen Free) W: SOIC (JEDEC) (Lead Free, Halogen Free) X: SOIC (EIAJ) (Lead Free, Halogen Free) G: PLCC (Lead Free, Halogen Free) H13: TSOP (8 mm x 13.4 mm) (Lead Free, Halogen Free) 15: 150 ns 20: 200 ns 25: 250 ns 15. The device used in the above example is a CAT28LV65NI−25T (PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel). 16. Solder−plate (tin−lead) packages, contact Factory for availability. 17. −40°C to +125°C is available upon request. 18. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ORDERING INFORMATION Orderable Part Numbers (for Pb−Free Devices) CAT28LV65GI−15T CAT28LV65GI−20T CAT28LV65GI−25T CAT28LV65GA−15T CAT28LV65GA−20T CAT28LV65GA−25T CAT28LV65H13I15T CAT28LV65H13I20T CAT28LV65H13I25T CAT28LV65H13A15T CAT28LV65H13A20T CAT28LV65H13A25T CAT28LV65LI15 CAT28LV65LI20 CAT28LV65LI25 CAT28LV65LA15 CAT28LV65LA20 CAT28LV65LA25 CAT28LV65WI−15T CAT28LV65WI−20T CAT28LV65WI−25T CAT28LV65WA−15T CAT28LV65WA−20T CAT28LV65WA−25T CAT28LV65XI−15T CAT28LV65XI−20T CAT28LV65XI−25T CAT28LV65XA−15T CAT28LV65XA−20T CAT28LV65XA−25T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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