CAT34RC02
2-kb I2C Serial EEPROM, Serial Presence Detect
FEATURES
■ 400 kHz I2C bus compatible*
■ Schmitt trigger on SCL and SDA inputs
■ 1.7 to 5.5 volt operation
■ Low power CMOS technology
■ 16-byte page write buffer
■ 1,000,000 program/erase cycles
■ Hardware write protection for entire memory
■ 100 year data retention
■ Permanent and reversible software write
■ 8-pin TSSOP and TDFN packages
protection for lower 128 bytes
■ Industrial temperature range
DESCRIPTION
The CAT34RC02 is a 2-kb Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements. The CAT34RC02 features
a 16-byte page write buffer. The device operates via the
I2C bus serial interface and is available in 8-pin TSSOP
and TDFN packages.
PIN CONFIGURATION
FUNCTIONAL SYMBOL
TDFN Package (SP2, VP2)
VCC
A0 1
A1 2
A2 3
8 VCC
7 WP
6 SCL
VSS 4
5 SDA
SCL
A2, A1, A0
TSSOP Package (U, Y, GY)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
CAT34RC02
SDA
WP
VCC
WP
SCL
SDA
VSS
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
1.7 V to 5.5 V Power Supply
VSS
Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1052, Rev. O
CAT34RC02
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
Storage Temperature ........................ -65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ............ -2.0 V to VCC + 2.0 V
Voltage on A0 .................................................. -2.0 V to +12.0 V
VCC with Respect to VSS .............................. -2.0 V to +7.0 V
RELIABILITY CHARACTERISTICS(2)
Symbol
Parameter
Min
Units
Endurance
1,000,000
Program/ Erase Cycles
TDR(*)
Data Retention
100
Years
VZAP(*)
ESD Susceptibility
4000
Volts
Latch-up
100
mA
NEND
ILTH
(*)
(3)
(*) Page Mode, VCC = 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
VCC = 1.7 V to 5.5 V, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC
Power Supply Current (Read)
ICC
Min
Typ
Max
Units
fSCL = 100 kHz
1
mA
Power Supply Current (Write)
fSCL = 100 kHz
3
mA
ISB(4)
Standby Current (VCC = 5.0 V)
VIN = GND or VCC
1
µA
ILI
Input Leakage Current
VIN = GND to VCC
1
µA
ILO
Output Leakage Current
VOUT = GND to VCC
1
µA
VIL
Input Low Voltage
–1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
VOL1
Output Low Voltage (VCC = 3.0 V)
IOL = 3 mA
0.4
V
VOL2
Output Low Voltage (VCC = 1.7 V)
IOL = 1.5 mA
0.5
V
VHV
RSWP Set/Clear Overdrive
A0 High Voltage
VHV - VCC > 4.8 V
10
V
Max
Units
7
CAPACITANCE TA = 25°C, f = 400 kHz, VCC = 5 V
Symbol
Test
Conditions
CI/O(2)
Input/Output Capacitance (SDA)
VI/O = 0 V
8
pF
Input Capacitance (other pins)
VIN = 0 V
6
pF
ZWPL
WP Input Impedance
VIN < 0.5 V
5
70
kΩ
ZWPH
WP Input Impedance
VIN > VCC x 0.7
500
CIN
(2)
Min
Typ
kΩ
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin
may undershoot to no less than -2.0 V or overshoot to no more than VCC + 2.0 V, for periods of less than 20 ns. The maximum DC
voltage on address pin A0 is +12.0 V.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(3) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1.0 V to VCC + 1.0 V.
(4) Standby Current, ISB = 10 µA max at extended temperature range.
Doc. No. 1052, Rev. O
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT34RC02
A.C. CHARACTERISTICS
VCC = 1.7 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.7 V - 5.5 V
Min
Max
2.5 V - 5.5 V
Min
Max
Units
FSCL
Clock Frequency
100
400
kHz
TI(1)
Noise Suppression Time
Constant at SCL, SDA Inputs
100
100
ns
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
0.9
µs
tBUF(1)
Time the Bus Must be Free Before
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
tLOW
4.7
1.3
µs
4
0.6
µs
Clock Low Period
4.7
1.3
µs
tHIGH
Clock High Period
4
0.6
µs
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
µs
tHD:DAT
Data In Hold Time
0
0
ns
tSU:DAT
Data In Setup Time
250
100
ns
tR(1)
SDA and SCL Rise Time
1
0.3
µs
SDA and SCL Fall Time
300
300
ns
tF
(1)
tSU:STO
Stop Condition Setup Time
tDH
Data Out Hold Time
4
0.6
µs
100
100
ns
Power-Up Timing(1)(2)
Symbol
Parameter
tPUR
tPUW
Min
Typ
Max
Units
Power-up to Read Operation
1
ms
Power-up to Write Operation
1
ms
Max
Units
5
ms
Write Cycle Limits
Symbol
Parameter
tWR
Write Cycle Time
Min
The write cycle time is the time elapsed between the
STOP command (following the write instruction) and the
completion of the internal write cycle. During the internal
Typ
write cycle, SDA is released by the Slave and the device
does not acknowledge external commands.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1052, Rev. O
CAT34RC02
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The CAT34RC02 supports the I2C (2-wire) Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT34RC02
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master alone assigns those roles. A maximum of 8
devices may be connected to the bus as determined by
the device address inputs A0, A1, and A2.
SCL: Serial Clock
The serial clock input pin is used to clock all data
transfers into or out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer data into and out of the device. This pin is an
open drain output in transmit mode.
A0, A1, A2: Device Address Inputs
These inputs set the device address. When left floating,
the address pins are internally pulled to ground.
WP: Write Protect
This input, when grounded or left floating, allows write
operations to the entire memory. When this pin is tied to
VCC, the entire memory is write protected.
Figure 1. Bus Timing
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
Figure 2. Write Cycle Timing
SCL
8th Bit
Byte n
SDA
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1052, Rev. O
STOP BIT
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT34RC02
I2C BUS PROTOCOL
Device Addressing
The I2C bus consists of two ‘wires’, SCL and SDA. The
two ‘wires’ are connected to the supply (VCC) via pull-up
resistors. Master and Slave devices connect to the bus
via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
The Master initiates a data transfer by creating a START
condition on the bus. The Master then broadcasts an 8bit serial Slave address. The four most significant bits of
the Slave address (the ‘preamble’) are fixed to 1010
(Ah), for normal read/write operations and 0110 (6h) for
Software Write Protect (SWP) operations (Fig. 5). The
next three bits, A2, A1 and A0, select one of eight possible
Slave devices. The last bit, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed.
(1) Data transfer may be initiated only when the bus is
not busy (see A.C. Characteristics).
(2) During a data transfer, the data line must remain
stable whenever the SCL line is high. An SDA
transition while SCL is high will be interpreted as a
START or STOP condition.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle. The Slave will aslo
acknowledge the 8-bit byte address and every data byte
presented in WRITE mode. In READ mode the Slave
shifts out eight bits of data, and then ‘releases’ the SDA
line durng the 9th clock cycle. If the Master acknowledges
in the 9th clock cycle (by pulling down the SDA line), then
the Slave continues transmitting. When data transfer is
complete, the Master responds with a NoACK (it does
not acknowledge the last data byte) and the Slave stops
transmitting and waits for a STOP condition.
START Condition
The START Condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START condition acts as a ‘wake-up’ call for the
Slave devices. A Slave will not respond to commands
unless the MASTER generates a START condition.
STOP Condition
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP condition starts the internal write cycle, when
following a WRITE command and sends the Slave into
standby mode, when following a READ command.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
Normal Read and Write
R/W
Programming the Write
Protect Register
DEVICE ADDRESS
0
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
1
0
A2
A1
5
A0
Doc No. 1052, Rev. O
CAT34RC02
acknowledge the Slave address, as long as internal
write is in progress.
WRITE OPERATIONS
Byte Write
WRITE PROTECTION
In Byte Write mode the Master creates a START condition,
and then broadcasts the Slave address, byte address
and data to be written. The Slave acknowledges the
three bytes by pulling down the SDA line during the 9th
clock cycle following each byte. The Master creates a
STOP condition after the last ACK from the Slave, which
then starts the internal write operation (Fig. 6). During
internal write, the Slave will ignore any read/write request
from the Master.
Hardware Write Protection
With the WP pin held HIGH, the entire memory, as well
as the SWP flags are protected against WRITE operations
(Fig. 9). If the WP pin is left floating or is grounded. then
it has no impact on the operation of the CAT34RC02.
Software Write Protection
Page Write
The lower half of memory (first 128 bytes) can be
protected against WRITE operations by setting one of
two Software Write Protection (SWP) flags/switches.
The PSWP (Permanent Software Write Protection) flag
can be set but not cleared by the user. The RSWP
(Reversible Software Write Protection) flag can be set
and cleared by the user. Whereas the PSWP flag can be
set ‘in-system’, the RSWP flag is meant to be used
during testing. RSWP commands require the presence
of a very high voltage (higher than VCC) on address pin
A0 and fixed logic levels for the other two address pins.
The CAT34RC02 contains 256 bytes of data, arranged
in 16 pages of 16 bytes each. The page is selected by the
four most significant bits of the address byte presented
to the device after the Slave address, while the four least
significant bits point to the byte within the page. By
‘loading’ more than one data byte into the device, up to
an entire page can be written in one write cycle (Fig. 7).
The internal byte address counter will increment after
each data byte. If the Master transmits more than 16
data bytes, then earlier bytes will be overwritten by later
bytes in a ‘wrap-around’ fashion within the selected
page. The internal write cycle is started following the
STOP condition created by the Master.
The CAT34RC02 is shipped ‘unprotected’. The state of
the SWP flags can be read by issuing an ‘Immediate
Address Read’ command, with the Slave address
‘preamble’ set to 0110 (6h) instead of the ‘normal’ 1010
(Ah). A SWP READ will return the complemented versions
of the two flags in the last two slots of the resulting data
byte; the other six more significant bits in the data byte
have no meaning to the user (Fig. 11).
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT34RC02 is busy writing or is ready to accept
commands. Polling is implemented by sending a
‘Selective Read’ command (described under READ
OPERATIONS) to the device. The CAT34RC02 will not
Figure 6. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
S
DATA n
DATA n+1
S
T
O
P
DATA n+P
P
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1052, Rev. O
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT34RC02
The PSWP flag can be set (forever) by issuing a ‘Byte
Write’ command, with the Slave address preamble set to
‘6h’, followed by a ‘don’t care’ address, followed by ‘don’t
care’ data and a STOP condition. The CAT34RC02 will
acknowledge the Slave address, dummy byte address
and dummy data (Fig. 10). The PSWP flag will be
permanently set (after the internal write cycle is
completed).
command attempts to ‘reaffirm’ one of the two switches,
then the CAT34RC02 will not acknowledge the command
itself. In addition, the CAT34RC02 will not acknowledge
a ‘reaffirming’ SWP command, even if the WP pin is
LOW.
Power-On Reset (POR)
The CAT34RC02 incorporates Power-On Reset (POR)
circuitry which protects the device against malfunctioning
while VCC is lower than the recommended operating
voltage.
The SWP commands are shown in Table 1.
Table 1. SWP Commands
The device will power up into a read-only state and will
power-down into a reset state when VCC crosses the
POR level of ~1.3V.
Slave Address
PIN
Preamble
Device Address
R/W
W
Command
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
SWP
READ
A2
A1
A0
0
1
1
0
A2
A1
A0
1
RSWP SET
0
0
VHV
0
1
1
0
0
0
1
0
RSWP
CLEAR
0
1
VHV
0
1
1
0
0
1
1
0
A2
A1
A0
0
1
1
0
A2
A1
A0
0
PSWP SET
READ OPERATIONS
Immediate Address Read
In standby mode, the CAT34RC02 internal address
counter points to the data byte immediately following the
last byte accessed by a previous operation. If the
‘previous’ byte was the last byte in memory, then the
address counter will point to the first memory byte, etc.
If the CAT34RC02 decodes a Slave address with a ‘1’ in
the R/W bit position (Fig. 8), it will issue an ACK in the 9th
clock cycle, and will then transmit the data byte being
pointed at by the address counter. The Master can then
stop further transmission by issuing a NoACK, followed
by a STOP condition.
The CAT34RC02 will not acknowledge RSWP or PSWP
commands, once the PSWP flag is set. If the PSWP flag
is not set, but the WP pin is HIGH, then the CAT34RC02
will react to RSWP or PSWP commands as follows: if the
command attempts to ‘flip’ one of the two SWP switches,
then the CAT34RC02 will respond the same way the
regular memory would, i.e. the command and address
(in this case dummy) are acknowledged, but the data (in
this case dummy) will not be acknowledged; if the
Selective Read
The READ operation can also be started at an address
different from the one stored in the address counter. The
Figure 8. Immediate Address Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
S
P
A
C
K
DATA
N
O
A
C
K
SCL
SDA
8
9
8th Bit
DATA OUT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
NO ACK
7
STOP
Doc No. 1052, Rev. O
CAT34RC02
address counter can be ‘initialized’ by performing a
‘dummy’ WRITE operation (Fig. 12). The START
condition is followed by the Slave address (with the R/W
bit set to ‘0’) and the desired byte address. Instead of
following up with data, the Master then issues a 2nd
START, followed by the ‘Immediate Address Read’
sequence, as described earlier.
Sequential Read
If the Master acknowledges the 1st data byte transmitted
by the CAT34RC02, then the device will continue
transmitting as long as each data byte is acknowledged
by the Master (Fig. 13). If the end of memory is reached
during sequential READ, the address counter will ‘wraparound’ to the beginning of memory, etc. Sequential
READ works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting
byte address.
Figure 9. Memory Array
FFH
Hardware Write Protectable
(by connecting WP pin to
Vcc)
7FH
Software Write Protectable
(by setting the write
protect flags)
00H
Figure 10. Software Write Protect (Write)
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
BYTE
ADDRESS
DATA
XXXXXXXX
XXXXXXXX
A
C
K
A
C
K
P
A
C
K
X = Don't Care
* For PSWP A0 is at normal CMOS levels and for RSWP, A0 is at VHV which must be held high beyond the end
of the STOP condition (approximately 1µs of “overlap” is sufficient).
Doc. No. 1052, Rev. O
8
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT34RC02
Figure 11. Software Write Protect (Read)
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
RSWP
S
T
O
P
PSWP
SLAVE
ADDRESS
S
P
00 00 0 0
A
C
K
DATA
N
O
A
C
K
Figure 12. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
S
S
T
O
P
SLAVE
ADDRESS
S
A
C
K
P
A
C
K
A
C
K
DATA n
N
O
A
C
K
Figure 13. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc No. 1052, Rev. O
CAT34RC02
8-PAD TDFN 2X3 PACKAGE (VP2, SP2)
A
E
PIN 1 INDEX AREA
A1
D
D2
A2
A3
K
SYMBOL
MIN
NOM
MAX
A
A1
A2
A3
b
D
D2
E
E2
e
K
L
0.70
0.00
0.45
0.75
0.02
0.55
0.20 REF
0.25
2.00
0.80
0.05
0.65
0.18
1.90
1.27
2.90
1.23
3.00
E2
0.30
2.10
1.75
3.10
1.90
PIN 1 ID
L
0.50 TYP
0.20
0.30
b
0.40
0.50
e
3xe
NOTE:
1. ALL DIMENSIONS IN MM. ANGLES IN DEGREES.
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMNALS. COPLANARITY SHALL NOT EXCEED 0.08 MM.
3. WARPAGE SHALL NOT EXCEED 0.10 MM.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE NOT CONSIDERED AS SPECIAL CHARACTERISTIC.
TDFN2X3_(02).eps
Doc. No. 1052, Rev. O
10
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT34RC02
8-LEAD TSSOP (U, Y, GY)
3.0 + 0.1
-A8
5
7.72 TYP
4.16 TYP
6.4
4.4 + 0.1
-B(1.78 TYP)
3.2
0.42 TYP
0.65 TYP
0.2 C B A
1
4
LAND PATTERN RECOMMENDATION
ALL LEAD TIPS
PIN #1 IDENT.
SEE DETAIL A
1.1 MAX TYP
0.1 C
ALL LEAD TIPS
0.09 - 0.20 TYP
(0.9)
-C0.10 + 0.05 TYP
0.65 TYP
GAGE PLANE
0.19 - 0.30 TYP
0.3 M A B S C S
0.25
o
0-8
o
0.6+0.1
SEATING PLANE
DETAIL A
Notes:
1. Lead coplanarity is 0.004" (0.102mm) maximum.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc No. 1052, Rev. O
CAT34RC02
ORDERING INFORMATION
Prefix
CAT
Company ID
Device #
34RC02
Product
Number
Suffix
J
I
TE13
Temperature Range
I = Industrial (-40°C to +85°C)
Package
U: TSSOP
Y: TSSOP (Lead-free, Halogen-free)
SP2: TDFN
VP2: TDFN (Lead-free, Halogen-free)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
REV-E
Die Revision
34RC02: E
Tape & Reel
Notes:
(1) The device used in the above example is a CAT34RC02UI-TE13 REV E (TSSOP, Industrial Temperature, 1.7 Volt to 5.5 Volt
Operating Voltage, Tape & Reel)
Doc. No. 1052, Rev. O
12
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT34RC02
REVISION HISTORY
Date
Revision Comments
09/22/03
A
Initial Issue
12/09/03
B
Removed Automotive temperature range
Changed Industrial Temp to “ I” from “ Blank” in ordering information
01/12/04
C
Updated Features
Replaced Block Diagram with Functional Symbol
Updated Notes for Reliability Characteristics, D.C. Operating
Characteristics and Capacitance
Updated TDFN package
Updated packaging information to reflect new TDFN package
02/20/04
D
Re-labeled TDFN package to A0, A1, A2 instead of A1, A2, A3
03/22/04
E
Updated Absolute Max. Ratings
Updated DC Operating Characteristics
Updated Table 1 (SWP Commands)
Updated Fig 11
Added mechanical package drawings
Corrected TDFN drawing
03/31/04
F
Corrected table 1 SWP Commands
05/16/04
G
Update D.C. Operating Characteristics
Update Write Cycle Limits
Update Revision History
Update Rev Number
06/03/04
H
Update Die Revision in Ordering Information
Eliminate data sheet designation
Updated DC Operating Characteristics
06/07/04
I
Updated Write Cycle Limits
9/27/04
J
Added Power-On Reset (POR) description
Added VHV and deleted ∆VHV in DC Operating Characteristics
10/18/04
K
Updated DC Operating Characteristics & notes (removed Note 5)
1/11/05
L
Deleted DIP and SOIC packages in all areas
Deleted Extended temperature range in all areas
2/17/05
M
Update Reliability Characteristics table and notes
07/19/05
N
Update Ordering Information
08/05/05
O
Update 8-Pad TDFN 2X3 Package (VP2, SP2)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc No. 1052, Rev. O
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
MiniPot™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.caalyst-semiconductor.com
Publication #:
Revison:
Issue date:
1052
O
08/05/05
工商网监
湘ICP备2023018690号
