CAT5132

CAT5132 16 Volt Digitally Programmable Potentiometer (DPPt) with 128 Taps and I2C Interface Description http://onsemi.com The CAT5132 is a high voltage Digitally Programmable Potentiometer (DPP) with non−volatile wiper setting memory, operating like a mechanical potentiometer. The tap points between the 127 equal resistive elements are connected to the wiper output via CMOS switches. The switches are controlled by a 7−bit Wiper Control Register (WCR). The wiper setting can be stored in a 7−bit non−volatile Data Register (DR). The WCR is accessed via the I2C serial bus. Upon power−up, the WCR is set to mid−scale (1000000). After the power supply is stable, the contents of the DR are transferred to the WCR and the wiper is returned to the memorized setting. The CAT5132 has two voltage supplies: VCC, the digital supply and V+, the analog supply. V+ can be much higher than VCC, allowing for 16 V analog operations. The CAT5132 can be used as a potentiometer or as a two−terminal variable resistor. Features MSOP−10 Z SUFFIX CASE 846AE MARKING DIAGRAM ANBx YMR • • • • • • • • • • • • • Single Linear DPP with 128 Taps End−to−end Resistance of 10 kW, 50 kW or 100 kW I2C Interface Fast Up/Down Wiper Control Mode Non−volatile Wiper Setting Storage Automatic Wiper Setting Recall at Power−up Digital Supply Range (VCC): 2.7 V to 5.5 V Analog Supply Range (V+): +8 V to +16 V Low Standby Current: 15 mA 100 Year Wiper Setting Memory Industrial Temperature Range: −40°C to +85°C 10−pin MSOP Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant LCD Screen Adjustment Volume Control Mechanical Potentiometer Replacement Gain Adjustment Line Impedance Matching VCOM Setting Adjustments ANBU = CAT5132ZI-10-GT3 ANBK = CAT5132ZI-50-GT3 ANBP = CAT5132ZI-00-GT3 Y = Production Year (Last Digit) M = Production Month (1-9, A, B, C) R = Production Revision PIN CONFIGURATION SDA GND VCC A1 A0 (Top View) 1 SCL V+ RL RW RH Applications • • • • • • ORDERING INFORMATION Device CAT5132ZI−10−GT3 CAT5132ZI−50−GT3 CAT5132ZI−00−GT3 MSOP (Pb−Free) 3,000 / Tape & Reel Package Shipping © Semiconductor Components Industries, LLC, 2010 July, 2010 − Rev. 5 1 Publication Order Number: CAT5132/D CAT5132 VCC SDA SCL A0 A1 128 TAP POSITION DECODE CONTROL 7−BIT NONVOLATILE MEMORY REGISTER (DR) 7−BIT WIPER CONTROL REGISTER (WCR) 0 CONTROL LOGIC AND ADDRESS DECODE 127 RESISTIVE ELEMENTS V+ 127 RH RL RW Figure 1. Block Diagram Table 1. PIN FUNCTION DESCRIPTION Pin No. 1 2 3 4 5 6 7 8 9 10 Pin Name SDA GND VCC A1 A0 RH RW RL V+ SCL Description Serial Data Input/Output − Bidirectional Serial Data pin used to transfer data into and out of the CAT5132. This is an Open−Drain I/O and can be wire OR’d with other Open−Drain (or Open Collector) I/Os. Ground Digital Supply Voltage (2.7 V to 5.5 V) Address Select Input to select slave address for I2C bus. Address Select Input to select slave address for I2C bus. High Reference Terminal for the potentiometer Wiper Terminal for the potentiometer Low Reference Terminal for the potentiometer Analog Supply Voltage for the potentiometer (+8.0 V to 16.0 V) Serial Bus Clock input for the I2C Serial Bus. This clock is used to clock all data transfers into and out of the CAT5132 Table 2. ABSOLUTE MAXIMUM RATINGS Rating Temperature Under Bias Storage Temperature Voltage on any SDA, SCL, A0 & A1 pins with respect to Ground (Note 1) Voltage on RH, RL & RW pins with respect to Ground VCC with respect to Ground V+ with respect to Ground Wiper Current (10 sec) Lead Soldering temperature (10 sec) Value −55 to +125 −65 to +150 −0.3 to VCC + 0.3 V+ −0.3 to +6 −0.3 to +16.5 ±6 +300 V V mA °C Unit °C °C V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −0.3 V to VCC +0.3 V. Table 3. RECOMMENDED OPERATING CONDITIONS Rating VCC V+ Operating Temperature Range Value +2.7 to +5.5 +8.0 to +16 −40 to +85 Unit V V °C http://onsemi.com 2 CAT5132 Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol RPOT RPOT RPOT RTOL IW RW VTERM RES ALIN RLIN TCRPOT TCRatio fc Parameter Potentiometer Resistance (100 kW) Potentiometer Resistance (50 kW) Potentiometer Resistance (10 kW) Potentiometer Resistance Tolerance Power Rating Wiper Current Wiper Resistance IW = ±1 mA @ V+ = 12 V IW = ±1 mA @ V+ = 8 V Voltage on RW, RH or RL Resolution Absolute Linearity (Note 3) Relative Linearity (Note 4) Temperature Coefficient of RPOT Ratiometric Temperature Coefficient VW(n)(actual) − VW(n)(expected) (Notes 6, 7) VW(n+1) − [VW(n) + LSB] (Notes 6, 7) (Note 2) (Note 2) (Note 2) RPOT = 50 kW 10/10/25 0.4 ±300 30 GND = 0 V; V+ = 8 V to 16 V GND 0.78 ±1 ±0.5 70 110 25°C Test Conditions Min Typ 100 50 10 ±20 50 ±3 150 200 V+ Max Units kW kW kW % mW mA W W V % LSB (Note 5) LSB (Note 5) ppm/°C ppm/°C pF MHz CH/CL/CW Potentiometer Capacitances Frequency Response 2. This parameter is tested initially and after a design or process change that affects the parameter. 3. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 4. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. 5. LSB = (RHM − RLM)/127; where RHM and RLM are the highest and lowest measured values on the wiper terminal. 6. n = 1, 2, ..., 127 7. V+ @ RH; 0 V @ RL; VW measured @ RW with no load. http://onsemi.com 3 CAT5132 Table 5. D.C. ELECTRICAL CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol ICC1 ICC2 ISB(VCC) ISB(V+) ILI ILO VIL VIH VOL1 Parameter Power Supply Current (Volatile Write/Read) Power Supply Current (Nonvolatile WRITE) Standby Current (VCC = 5 V) V+ Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0) IOL = 3 mA Test Conditions FSCL = 400 kHz, SDA Open, VCC = 5.5 V, Input = GND FSCL = 400 kHz, SDA Open, VCC = 5.5 V, Input = GND VIN = GND or VCC, SDA = VCC VCC = 5 V, V+ = 16 V VIN = GND to VCC VOUT = GND to VCC −1 VCC x 0.7 Min Max 1 3.0 5 10 10 10 VCC x 0.3 VCC + 1.0 0.4 Units mA mA mA mA mA mA V V V Table 6. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5.0 V) Symbol CI/O CIN Parameter Input/Output Capacitance (SDA) Input Capacitance (A0, A1, SCL) Test Conditions VI/O = 0 V (Note 8) VIN = 0 V (Note 8) Min Max 8 6 Units pF pF Table 7. A.C. CHARACTERISTICS VCC = 2.7 − 5.5 V Symbol FSCL TI (Note 8) tAA tBUF (Note 8) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tR (Note 8) tF (Note 8) tSU:STO tDH Clock Frequency Noise Suppression Time Constant at SCL & SDA Inputs SLC Low to SDA Data Out and ACK Out Time the bus must be free before a new transmission can start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data in Hold Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Conditions Setup Time Data Out Hold Time 0.6 100 1.2 0.6 1.2 0.6 0.6 0 0.3 300 Parameter (see Figure 6) Min Max 400 50 1 Units kHz ns ms ms ms ms ms ms ns ms ns ms ns 8. This parameter is tested initially and after a design or process change that affects the parameter. http://onsemi.com 4 CAT5132 Table 8. POWER UP TIMING (Notes 9, 10) Symbol tPUR tPUW Power−up to Read Operation Power−up to Write Operation Parameter Min Max 1 1 Units ms ms Table 9. WIPER TIMING Symbol tWRPO tWRL Parameter Wiper Response Time After Power Supply Stable Wiper Response Time After Instruction Issued Min 5 5 Max 10 10 Units ms ms Table 10. WRITE CYCLE LIMITS Symbol tWR Write Cycle Time (see Figure 7) Parameter Min Max 5 Units ms The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. Table 11. RELIABILITY CHARACTERISTICS Symbol NEND (Note 9) TDR (Note 9) Parameter Endurance Data Retention Reference Test Method MIL−STD−883, Test Method 1033 MIL−STD−883, Test Method 1008 Min 100,000 100 Max Units Cycles Years 9. This parameter is tested initially and after a design or process change that affects the parameter. 10. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. http://onsemi.com 5 CAT5132 TYPICAL PERFORMANCE CHARACTERISTICS 12 10 8 RWL (KW) 6 4 2 0 ICC2 (mA) VCC = 2.7 V; V+ = 8 V VCC = 5.5 V; V+ = 16 V 400 350 300 250 200 150 100 50 0 16 32 48 64 80 96 112 128 0 −50 −30 −10 10 30 50 70 90 110 130 VCC = 2.7 V VCC = 5.5 V TAP POSITION TEMPERATURE (°C) Figure 2. Resistance between RW and RL 1.0 0.8 0.6 ALIN ERROR (LSB) 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1.0 VCC = 2.7 V; V+ = 8 V VCC = 5.5 V; V+ = 16 V 0 16 32 48 64 80 96 112 128 Tamb = 25°C Rtotal = 10 K ALIN ERROR (LSB) 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 Figure 3. ICC2 (NV Write) vs. Temperature Tamb = 25°C Rtotal = 10 K VCC = 2.7 V; V+ = 8 V VCC = 5.5 V; V+ = 16 V 0 16 32 48 64 80 96 112 128 TAP POSITION TAP POSITION Figure 4. Absolute Linearity Error per Tap Position Figure 5. Relative Linearity Error http://onsemi.com 6 CAT5132 tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tDH tBUF tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW tR Figure 6. Bus Timing SCL SDA 8TH BIT BYTE n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Write Cycle Timing http://onsemi.com 7 CAT5132 Serial Bus Protocol The following defines the features of the I2C bus protocol: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5132 will be considered a slave device in all applications. START Condition Acknowledge The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT5132 monitors the SDA and SCL lines and will not respond until this condition is met (see Figure 8). STOP Condition After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data (see Figure 9). The CAT5132 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8−bit byte. When the CAT5132 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5132 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. Acknowledge Polling A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition (see Figure 8). The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the STOP condition is issued to indicate the end of the write operation, the CAT5132 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the START condition followed by the slave address. If the CAT5132 is still busy with the write operation, no ACK will be returned. If the CAT5132 has completed the write operation, an ACK will be returned and the host can then proceed with the next instruction operation. SCL SDA START CONDITION STOP CONDITION Figure 8. Start/Stop Condition BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK DELAY (≤ tAA) 1 8 9 BUS RELEASE DELAY (RECEIVER) ACK SETUP (≥ tSU:DAT) Figure 9. Acknowledge Condition http://onsemi.com 8 CAT5132 Device Description Access Control Register The volatile register WCR and the non−volatile register DR are accessed only by addressing the volatile Access Register AR first, using the 3 byte I2C protocol for all read and write operations (see Table 12). The first byte is the slave address/instruction byte (see details below). The second byte contains the address (02h) of the AR register. The data in the third byte controls which register WCR (80h) or DR (00h) is being addressed (see Figure 10). Slave Address Instruction Byte Description The first byte sent to the CAT5132 from the master processor is called the Slave/DPP Address Byte. The most significant five bits of the slave address are a device type identifier. For the CAT5132 these bits are fixed at 01010 (refer to Table 13). Table 12. ACCESS CONTROL REGISTER START A1 A0 The next two bits, A1 and A0, are the internal slave address and must match the physical device address which is defined by the state of the A1 and A0 input pins. Only the device with slave address matching the input byte will be accessed by the master. This allows up to 4 devices to reside on the same bus. The A1 and A0 inputs can be actively driven by CMOS input signals or tied to VCC or Ground. The last bit is the READ/WRITE bit and determines the function to be performed. If it is a “1” a read command is initiated and if it is a “0” a write is initiated. For the AR register only write is allowed. After the Master sends a START condition and the slave address byte, the CAT5132 monitors the bus and responds with an acknowledge when its address matches the transmitted slave address. AR address − 02h 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 WCR(80h) / DR(00h) selection 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST ST 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 A A A A A A SP SP Table 13. BYTE 1 SLAVE ADDRESS AND INSTRUCTION BYTE Device Type Identifier ID4 0 (MSB) ID3 1 ID2 0 ID1 1 ID0 0 Slave Address A1 X A0 X Read/Write R/W X (LSB) BUS ACTIVITY: MASTER SDA LINE S T A R T S SLAVE ADDRESS & INSTRUCTION FIXED AR REGISTER ADDRESS WCR/DR SELECTION S T O P P A C K VARIABLE A C K A C K Figure 10. Access Register Addressing Using 3 Bytes http://onsemi.com 9 STOP 1st byte ACK ID4 ID3 ID2 ID1 ID0 Wb 2nd byte ACK 3rd byte ACK CAT5132 Wiper Control Register (WCR) Description The CAT5132 contains a 7−bit Wiper Control Register which is decoded to select one of the 128 switches along its resistor array. The WCR is a volatile register and is written with the contents of the nonvolatile Data Register (DR) on power−up. The Wiper Control Register loses its contents when the CAT5132 is powered−down. The contents of the WCR may be read or changed directly by the host using a READ/WRITE command after addressing the WCR (see Table 12 to access WCR). Since the CAT5132 will only Table 14. WCR WRITE OPERATION START A1 A0 1st byte ACK ID4 ID3 ID2 ID1 ID0 Wb 2nd byte make use of the 7 LSB bits (The first data bit, or MSB, is ignored) on write instructions and will always come back as a “0” on read commands. A write operation (see Table 14) requires a Start condition, followed by a valid slave address byte, a valid address byte 00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge. At this time the data is written only to volatile registers, then the device enters its standby state. 3rd byte ACK WCR(80h) selection 1 0 0 0 0 0 0 0 ACK A x x ACK x A 0 0 0 ACK A 0 0 0 0 ACK A 0 0 AR address − 02h 0 0 0 0 0 0 1 0 ST START 0 1 0 1 0 0 0 0 A A SP ACK ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 ACK slave address byte WCR address − 00h data byte x x x x x A SP An increment operation (see Table 15) requires a Start condition, followed by a valid increment address byte (01011), a valid address byte 00h. After each of the two bytes, the CAT5132 responds with an acknowledge. At this time if the data is high then the wiper is incremented or if the Table 15. WCR INCREMENT/DECREMENT OPERATION START A1 A0 1st byte ACK ID4 ID3 ID2 ID1 ID0 Wb 2nd byte data is low the wiper is decremented at each clock. Once the stop is issued then the device enters its standby state with the WCR data as being the last inc/dec position. Also, the wiper position does not roll over but is limited to min and max positions. 3rd byte ACK WCR(80h) selection 1 0 0 0 0 AR address − 02h 0 0 0 0 0 0 1 0 ST START 0 1 0 1 0 0 0 0 A A SP ACK ST 0 1 0 1 1 0 0 0 A 0 0 0 0 0 0 0 0 ACK slave address byte WCR address − 00h increment (1) / decrement (0) bits 1 1 1 1 0 A SP A read operation (see Table 16) requires a Start condition, followed by a valid slave address byte for write, a valid address byte 00h, a second START and a second slave address byte for read. After each of the three bytes, the Table 16. WCR READ OPERATION START A1 A0 1st byte ACK ID4 ID3 ID2 ID1 ID0 Wb 2nd byte CAT5132 responds with an acknowledge and then the device transmits the data byte. The master terminates the read operation by issuing a STOP condition following the last bit of Data byte. 3rd byte ACK WCR(80h) selection 1 0 0 0 0 AR address − 02h 0 0 0 0 0 0 1 0 ST START 0 1 0 1 0 0 0 0 A A SP ST START 0 1 0 1 0 0 0 0 ACK slave address byte WCR address − 00h 0 0 0 0 0 0 0 0 STOP A slave address byte 0 1 0 1 0 0 0 1 A 0 X X data byte X X X X X ST SP http://onsemi.com 10 STOP STOP STOP STOP STOP CAT5132 Data Register (DR) The Data Register (DR) is a nonvolatile register and its contents are automatically written to the Wiper Control Register (WCR) on power−up. It can be read at any time without effecting the value of the WCR. The DR, like the WCR, only stores the 7 LSB bits and will report the MSB bit as a “0”. Writing to the DR is performed in the same fashion as the WCR except that a time delay of up to 5 ms is experienced while the nonvolatile store operation is being performed. During the internal non−volatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. The WCR is also Table 17. DR WRITE OPERATION START A1 A0 1st byte ACK ID4 ID3 ID2 ID1 ID0 Wb 2nd byte written during a write to DR. After a DR WRITE is complete the DR and WCR will contain the same wiper position. To write or read to the DR, first the access to DR is selected, see table 1 then the data is written or read using the following sequences. A write operation (see Table 17) requires a Start condition, followed by a valid slave address byte, a valid address byte 00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge. At this time the data is written both to volatile and non−volatile registers, then the device enters its standby state. 3rd byte ACK DR(00h) selection 0 0 0 0 0 0 0 0 ACK A X X ACK X A 0 0 0 ACK A AR address − 02h 0 0 0 0 0 0 1 0 ST START 0 1 0 1 0 0 0 0 A A SP ACK ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 ACK slave address byte DR address − 00h data byte X X X X X A SP A read operation (see Table 18) requires a Start condition, followed by a valid slave address byte, a valid address byte 00h, a second Start and a second slave address byte for read. After each of the three bytes the CAT5132 responds with an Table 18. DR READ OPERATION START A1 A0 1st byte ACK ID4 ID3 ID2 ID1 ID0 Wb 2nd byte acknowledge and then the device transmits the data byte. The master terminates the read operation by issuing a STOP condition following the last bit of Data byte. AR address − 02h 0 0 0 0 0 0 1 0 DR(00h) selection 0 0 0 0 0 ST START 0 1 0 1 0 0 0 0 A A SP ST START 0 1 0 1 0 0 0 0 ACK slave address byte DR address − 00h 0 0 0 0 0 0 0 0 STOP A slave address byte 0 1 0 1 0 0 0 1 A 0 X X data byte X X X X X ST SP http://onsemi.com 11 STOP 3rd byte ACK STOP STOP CAT5132 Potentiometer Operation Power−On The CAT5132 is a 128−position, digital controlled potentiometer. When applying power to the CAT5132, VCC must be supplied prior to or simultaneously with V+. At the same time, the signals on RH, RW and RL terminals should not exceed V+. If V+ is applied before VCC, the electronic switches of the DPP are powered in the absence of the switch control signals, that could result in multiple switches being turned on. This causes unexpected wiper settings and possible current overload of the potentiometer. When VCC is applied the device turns on at the mid−point wiper location (64) until the wiper register can be loaded with the nonvolatile memory location previously stored in the device. After the nonvolatile memory data is loaded into the wiper register the wiper location will change to the previously stored wiper position. At power−down, it is recommended to turn−off first the signals on RH, RW and RL, followed by V+ and, after that, VCC, in order to avoid unexpected transmissions of the wiper and uncontrolled current overload of the potentiometer. The end−to−end nominal resistance of the potentiometer has 128 contact points linearly distributed across the total resistor. Each of these contact points is addressed by the 7 bit wiper register which is decoded to select one of these 128 contact points. Each contact point generates a linear resistive value between the 0 position and the 127 position. These values can be determined by dividing the end−to−end value of the potentiometer by 127. In the case of the 10 kW potentiometer ~79 W is the resistance between each wiper position. However in addition to the ~79 W for each resistive segment of the potentiometer, a wiper resistance offset must be considered. Table 19 shows the effect of this value and how it would appear on the wiper terminal. This offset will appear in each of the CAT5132 end−to−end resistance values in the same way as the 10 kW example. However resistance between each wiper position for the 50 kW version will be ~395 W and for the 100 kW version will be ~790 W. Table 19. POTENTIOMETER RESISTANCE AND WIPER RESISTANCE OFFSET EFFECTS Position 00 01 63 127 Typical RW to RL Resistance for 10 kW DPP 70 W or 149 W or 5,047 W or 10,070 W or 0 W + 70 W 79 W + 70 W 4,977 W + 70 W 10,000 W + 70 W Position 00 64 126 127 Typical RW to RH Resistance for 10 kW DPP 10,070 W or 5,047 W or 149 W or 70 W or 10,000 W + 70 W 4,977 W + 70 W 79 W + 70 W 0 W + 70 W http://onsemi.com 12 CAT5132 PACKAGE DIMENSIONS MSOP 10, 3x3 CASE 846AE−01 ISSUE O SYMBOL A A1 A2 b c E E1 D E E1 e L L1 L2 MIN NOM MAX 1.10 0.00 0.75 0.17 0.13 2.90 4.75 2.90 0.40 0.05 0.85 0.15 0.95 0.27 0.23 3.00 4.90 3.00 0.50 BSC 0.60 0.95 REF 0.25 BSC 3.10 5.05 3.10 0.80 θ TOP VIEW 0º 8º DETAIL A D A A2 A1 e SIDE VIEW b c END VIEW q L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A http://onsemi.com 13 CAT5132 Example of Ordering Information (Note 13) Prefix CAT Device # 5132 Suffix Z I −10 −G T3 Company ID (Optional) Product Number 5132 Package Z: MSOP Temperature Range I = Industrial (−40°C to +85°C) Lead Finish G: NiPdAu (PPF) Tape & Reel (Note 15) T: Tape & Reel 3: 3,000 Units / Reel Resistance −10: 10 kW −50: 50 kW −00: 100 kW 11. All packages are RoHS compliant (Lead−free, Halogen−free). 12. The standard lead finish is NiPdAu. 13. The device used in the above example is a CAT5132ZI−10−GT3 (MSOP, Industrial Temperature range, 10 kW, NiPdAu, Tape & Reel, 3,000/Reel). 14. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 15. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. DPP is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 14 CAT5132/D