CAT5221WI-10-TE13

H CAT5221 EE GEN FR ALO Dual Digitally Programmable Potentiometers (DPP™) with 64 Taps and 2-wire Interface LE A D F R E ETM FEATURES ■ Automatic recall of saved wiper settings at ■ Two linear-taper digitally programmable power up potentiometers ■ 64 resistor taps per potentiometer ■ 2.5 to 6.0 volt operation ■ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ ■ Standby current less than 1µA ■ Potentiometer control and memory access via ■ 1,000,000 nonvolatile WRITE cycles 2-wire interface (I2C like) ■ 100 year nonvolatile memory data retention Ω ■ Low wiper resistance, typically 80Ω ■ 20-lead SOIC and TSSOP packages ■ Nonvolatile memory storage for up to four wiper ■ Industrial temperature ranges settings for each potentiometer DESCRIPTION wiper control register or any of the non-volatile data registers is via a 2-wire serial bus (I2C-like). On powerup, the contents of the first data register (DR0) for each of the four potentiometers is automatically loaded into its respective wiper control register (WCR). The CAT5221 is two Digitally Programmable Potentiometers (DPPs™) integrated with control logic and 16 bytes of NVRAM memory. Each DPP consists of a series of 63 resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 6-bit control register (WCR) independently controls the wiper tap switches for each DPP. Associated with each wiper control register are four 6-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the The CAT5221 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. FUNCTIONAL DIAGRAM PIN CONFIGURATION RH0 SOIC Package (J, W) TSSOP Package (U, Y) VCC NC RW0 RL0 1 20 2 19 RH0 A0 3 18 NC 4 17 NC A2 RW1 RL1 5 CAT 16 5221 15 A1 A3 7 14 SCL RH1 8 13 NC SDA 9 12 NC GND 10 11 NC 6 SCL SDA 2-WIRE BUS INTERFACE WIPER CONTROL REGISTERS R W0 R W1 A0 A1 A2 A3 CONTROL LOGIC NONVOLATILE DATA REGISTERS RL0 © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice RH1 1 RL1 Document No. 2113, Rev. I CAT5221 PIN DESCRIPTION PIN DESCRIPTIONS Pin (SOIC) Name 1 RW0 Wiper Terminal for Potentiometer 0 2 RL0 Low Reference Terminal for Potentiometer 0 3 RH0 High Reference Terminal for Potentiometer 0 4 A0 Device Address, LSB 5 A2 Device Address 6 RW1 Wiper Terminal for Potentiometer 1 7 RL1 Low Reference Terminal for Potentiometer 1 8 RH1 High Reference Terminal for Potentiometer 1 SCL: Serial Clock The CAT5221 serial clock input pin is used to clock all data transfers into or out of the device. Function 9 SDA Serial Data Input/Output 10 GND Ground 11 NC No Connect 12 NC No Connect 13 NC No Connect 14 SCL Bus Serial Clock 15 A3 Device Address 16 A1 Device Address 17 NC No Connect 18 NC No Connect 19 NC No Connect 20 VCC SDA: Serial Data The CAT5221 bidirectional serial data pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wireOR'd with the other open drain or open collector outputs. A0, A1, A2, A3: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of sixteen devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5221. RH, RL: Resistor End Points The two sets of RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Wiper RW: The two RW pins are equivalent to the wiper terminal of a mechanical potentiometer. Supply Voltage DEVICE OPERATION The CAT5221 is two resistor arrays integrated with 2wire serial interface logic, two 6-bit wiper control registers and eight 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a Document No. 2113, Rev. I CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. Additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode. 2 CAT5221 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Respect toVSS(1)(2) ................. -2.0V to +VCC +2.0V *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. VCC with Respect to Ground ................ -2.0V to +7.0V Recommended Operating Conditions: Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W VCC = +2.5V to +6.0V Temperature Under Bias .................. -55°C to +125°C Storage Temperature ........................ -65°C to +150°C Temperature Industrial Lead Soldering Temperature (10 secs) ............ 300°C Min -40°C Max 85°C Wiper Current .................................................. +12mA Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. POTENTIOMETER CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter Test Conditions Min Typ Max Units RPOT Potentiometer Resistance (-00) 100 kΩ RPOT Potentiometer Resistance (-50) 50 kΩ RPOT Potentiometer Resistance (-10) 10 kΩ RPOT Potentiometer Resistance (-2.5) 2.5 kΩ Potentiometer Resistance Tolerance +20 % RPOT Matching 1 % 50 mW +6 mA 300 Ω 150 Ω VCC V Power Rating 25°C, each pot IW Wiper Current RW Wiper Resistance IW = +3mA @ VCC =3V RW Wiper Resistance IW = +3mA @ VCC = 5V VTERM Voltage on any RH or RL Pin VSS = 0V VN Noise (1) Resolution 80 GND TBD nV/ Hz 1.6 % Absolute Linearity (2) Rw(n)(actual)-R(n)(expected)(5) +1 LSB (4) Relative Linearity (3) Rw(n+1)-[Rw(n)+LSB](5) +0.2 LSB (4) TCRPOT Temperature Coefficient of RPOT (1) TCRATIO Ratiometric Temp. Coefficient (1) Potentiometer Capacitances (1) CH/CL/CW fc Frequency Response RPOT = 50kΩ(1) +300 ppm/°C 20 ppm/°C 10/10/25 pF 0.4 MHz Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (4) LSB = RTOT / 63 or (RH - RL) / 63, single pot (5) n = 0, 1, 2, ..., 63 3 Document No. 2113, Rev. I CAT5221 D.C. OPERATING CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter Test Conditions Min Typ Max Units fSCL = 400kHz 1 mA VIN = GND or VCC; SDA Open 1 µA VIN = GND to VCC 10 µA VOUT = GND to VCC 10 µA ICC Power Supply Current ISB Standby Current (VCC = 5.0V) ILI Input Leakage Current ILO Output Leakage Current VIL Input Low Voltage -1 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 1.0 V 0.4 V Max Units VOL1 Output Low Voltage (VCC = 3.0V) IOL = 3 mA CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test CI/O (1) CIN(1) Conditions Min Typ Input/Output Capacitance (SDA) VI/O = 0V 8 pF Input Capacitance (A0, A1, A2, A3, SCL) VIN = 0V 6 pF Max Units A.C. CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter Min Typ fSCL Clock Frequency 400 kHz TI(1) Noise Suppression Time Constant at SCL, SDA Inputs 50 ns tAA SLC Low to SDA Data Out and ACK Out 0.9 µs tBUF(1) Time the Bus Must Be Free Before a New Transmission Can Start 1.2 µs tHD:STA Start Condition Hold Time 0.6 µs tLOW Clock Low Period 1.2 µs tHIGH Clock High Period 0.6 µs tSU:STA Start Condition SetupTime (For a Repeated Start Condition) 0.6 µs tHD:DAT Data in Hold Time 0 ns tSU:DAT Data in Setup Time 100 ns tR(1) SDA and SCL Rise Time 0.3 µs tF(1) SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Out Hold Time 50 ns POWER UP TIMING (1) Over recommended operating conditions unless otherwise stated. Symbol Parameter Min Typ Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Document No. 2113, Rev. I 4 CAT5221 WRITE CYCLE LIMITS Over recommended operating conditions unless otherwise stated. Symbol tWR Parameter Min Typ Write Cycle Time Max Units 5 ms The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. RELIABILITY CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter Reference Test Method Min NEND(1) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH(1)(2) Latch-Up JEDEC Standard 17 100 mA TDR (1) Typ Max Units Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Figure 1. Bus Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 2. Write Cycle Timing SCL SDA 8TH BIT ACK BYTE n tWR STOP CONDITION START CONDITION ADDRESS Figure 3. Start/Stop Timing SDA SCL START BIT STOP BIT 5 Document No. 2113, Rev. I CAT5221 SERIAL BUS PROTOCOL the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 0101 for the CAT5221 (see Figure 5). The next four significant bits (A3, A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to sixteen devices may be individually addressed by the system. Typically, +5V and ground are hard-wired to these pins to establish the device's address. The following defines the features of the 2-wire bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. After the Master sends a START condition and the slave address byte, the CAT5221 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5221 will be considered a slave device in all applications. Acknowledge START Condition After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT5221 monitors the SDA and SCL lines and will not respond until this condition is met. The CAT5221 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. STOP Condition When the CAT5221 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5221 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master then sends the address of Figure 4. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START Document No. 2113, Rev. I 6 CAT5221 Acknowledge Polling WRITE OPERATIONS The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the CAT5221 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address. If the CAT5221 is still busy with the write operation, no ACK will be returned. If the CAT5221 has completed the write operation, an ACK will be returned and the host can then proceed with the next instruction operation. In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte that defines the requested operation of CAT5221. The instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the selected register. The CAT5221 acknowledges once more and the Master generates the STOP condition, at which time if a nonvolatile data register is being selected, the device begins an internal programming cycle to non-volatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Figure 5. Slave Address Bits CAT5221 * ** 0 1 0 1 A3 A2 A1 A0 A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device. A0, A1, A2 and A3 must compare to its corresponding hard wired input pins. Figure 6. Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T INSTRUCTION BYTE SLAVE/DPP ADDRESS Fixed Variable op code Pot/WCR Data Register Address Address S T O P DR WCR DATA S P A C K A C K 7 A C K Document No. 2113, Rev. I CAT5221 INSTRUCTION AND REGISTER DESCRIPTION INSTRUCTION BYTE The next byte sent to the CAT5221 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I [3:0]. The P0 bit points to one of the Wiper Control Registers. The least two significant bits, R1 and R0, point to one of the four data registers of each associated potentiometer. The format is shown in Table 2. Instructions SLAVE ADDRESS BYTE The first byte sent to the CAT5221 from the master/ processor is called the Slave/DPP Address Byte. The most significant four bits of the slave address are a device type identifier. These bits for the CAT5221 are fixed at 0101[B] (refer to Table 1). Data Register Selection Data Register Selected The next four bits, A3 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 - A0 input pins for the CAT5221 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. R1 R0 DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1 Table 1. Identification Byte Format Device Type Identifier Slave Address ID3 ID2 ID1 ID0 0 1 0 1 A3 A2 A1 (MSB) A0 (LSB) Table 2. Instruction Byte Format Instruction Opcode I3 (MSB) Document No. 2113, Rev. I I2 WCR/Pot Selection I1 0 I0 8 P0 Data Register Selection R1 R0 (LSB) CAT5221 four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Registers is a non-volatile operation and will take a maximum of 5ms. WIPER CONTROL AND DATA REGISTERS Wiper Control Register (WCR) The CAT5221 contains two 6-bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 64 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction, it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (DR0) upon power-up. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as standard memory locations for system parameters or user preference data. INSTRUCTIONS Four of the nine instructions are three bytes in length. These instructions are: — Read Wiper Control Register - read the current wiper position of the selected potentiometer in the WCR — Write Wiper Control Register - change current wiper position in the WCR of the selected potentiometer The Wiper Control Register is a volatile register that loses its contents when the CAT5221 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. — Read Data Register - read the contents of the selected Data Register Data Registers (DR) — Write Data Register - write a new value to the selected Data Register Each potentiometer has four 6-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the The basic sequence of the three byte instructions is illustrated in Figure 8. These three-byte instructions Table 3. Instruction Set Instruction Set Instruction Read Wiper Control Register Write Wiper Control Register I3 I2 I1 I0 0 WCR0/ P0 R1 R0 1 0 0 1 0 1/0 0 0 1 0 1 0 0 1/0 0 0 Read Data Register 1 0 1 1 0 1/0 1/0 1/0 Write Data Register 1 1 0 0 0 1/0 1/0 1/0 XFR Data Register to Wiper Control Register 1 1 0 1 0 1/0 1/0 1/0 XFR Wiper Control Register to Data Register 1 1 1 0 0 1/0 1/0 1/0 Global XFR Data Registers to Wiper Control Registers 0 0 0 1 0 0 1/0 1/0 Global XFR Wiper Control Registers to Data Register 1 0 0 0 0 0 1/0 1/0 Increment/Decrement Wiper Control Register 0 0 1 0 0 1/0 0 0 Note: Operation Read the contents of the Wiper Control Register pointed to by P0 Write new value to the Wiper Control Register pointed to by P0 Read the contents of the Data Register pointed to by P0 and R1-R0 Write new value to the Data Register pointed to by P0 and R1-R0 Transfer the contents of the Data Register pointed to by P0 and R1-R0 to its associated Wiper Control Register Transfer the contents of the Wiper Control Register pointed to by P0 to the Data Register pointed to by R1-R0 Transfer the contents of the Data Registers pointed to by R1-R0 of all four pots to their respective Wiper Control Register s Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1-R0 of all four pots Enable Increment/decrement of the Control Latch pointed to by P0 1/0 = data is one or zero 9 Document No. 2113, Rev. I CAT5221 exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a maximum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. — Global XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. — Global XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. Four instructions require a two-byte sequence to complete, as illustrated in Figure 7. These instructions transfer data between the host/processor and the CAT5221; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 5 and 9). The Increment/Decrement command is different from the other commands. Once the command is issued and the CAT5221 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. — XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. — XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Control Register to the specified associated Data Register. See Instructions format for more detail. Figure 7. Two-Byte Instruction Sequence SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 A2 A1 A0 T A Internal R Device ID Address T A I3 C K I2 I1 I0 Instruction Opcode 0 P0 R1 R0 A C K Pot/WCR Register Address Address S T O P Figure 8. Three-Byte Instruction Sequence SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 T A Device ID R T A2 A0 A I3 C K Internal Address A1 I2 I1 I0 Instruction Opcode R1 R0 A C K Pot/WCR Data Address Register Address 0 P0 D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register D[7:0] A C K S T O P Figure 9. Increment/Decrement Instruction Sequence 0 SDA S T A R T 1 0 1 ID3 ID2 ID1 ID0 Device ID Document No. 2113, Rev. I A3 A2 A1 A0 Internal Address A C K I3 I2 I1 Instruction Opcode 10 I0 0 P0 R1 R0 Pot/WCR Data Address Register Address A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P CAT5221 Figure 10. Increment/Decrement Timing Limits INC/DEC Command Issued tWRID SCL SDA Voltage Out RW INSTRUCTION FORMAT Read Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 0 0 1 0 P0 0 0 A C K 4 3 2 1 0 A C K S T O P DATA A C 2 1 0 K S T O P A C 2 1 0 K S T O P A C 2 1 0 K S T O P DATA 7 6 5 Write Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 0 1 0 0 P0 0 0 A C K 7 6 5 4 3 Read Data Register (DR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K A C 1 0 1 1 0 P0 R1 R0 7 6 K A C K A C 1 1 0 0 0 P0 R1 R0 7 6 K INSTRUCTION DATA 5 4 3 Write Data Register (DR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 INSTRUCTION 11 DATA 5 4 3 Document No. 2113, Rev. I CAT5221 INSTRUCTION FORMAT (continued) Global Transfer Data Register (DR) to Wiper Control Register (WCR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS A C 0 0 0 1 0 0 R1 R0 K INSTRUCTION S T O P Global Transfer Wiper Control Register (WCR) to Data Register (DR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS INSTRUCTION 1 0 0 0 0 0 R1 R0 A C K S T O P Transfer Wiper Control Register (WCR) to Data Register (DR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS A C 1 1 1 0 0 P0 R1R0 K INSTRUCTION S T O P Transfer Data Register (DR) to Wiper Control Register (WCR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS A C 1 1 0 1 0 P0 R1R0 K INSTRUCTION S T O P Increment (I)/Decrement (D) Wiper Control Register (WCR) S T A R T A INSTRUCTION C 0 1 0 1 A3 A2 A1 A0 0 0 1 0 0 P0 0 0 K DEVICE ADDRESS A C K DATA I/D I/D • • • A C I/D I/D K Notes: (1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued. Document No. 2113, Rev. I 12 S T O P CAT5221 ORDERING INFORMATION 5221 Package J: SOIC U: TSSOP W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Notes: (1) The device used in the above example is a CAT5221JI-10-TE13 (SOIC, Industrial Temperature, 10kohm, Tape & Reel) 13 Document No. 2113, Rev. I CAT5221 PACKAGING INFORMATION 20-LEAD 300 MIL WIDE SOIC (J, W) 0.2914 (7.40) 0.2992 (7.60) 0.394 (10.00) 0.419 (10.65) 0.5985 (15.20) 0.6141 (15.60) 0.0926 (2.35) 0.1043 (2.65) 0.050 (1.27) BSC 0.0040 (0.10) 0.0118 (0.30) 0.013 (0.33) 0.020 (0.51) 0.010 (0.25) X 45 0.029 (0.75) 0.0091 (0.23) 0.0125 (0.32) 0 —8 0.016 (0.40) 0.050 (1.27) Document No. 2113, Rev. I 14 CAT5221 20-LEAD TSSOP (U, Y) 1.0 E E1 DETAIL A 1.0 A A b A1 0.076MM SEATING PLANE A A2 D e θ2 0.20 R1 SYMBOL R DIMENSION IN MM MIN NOM A GAUGE PLANE θ1 L θ3 L1 DETAIL A c c1 b MAX .043 0.05 0.15 .002 A2 0.80 0.90 1.05 .031 .035 .041 L 0.50 0.60 0.75 .020 .024 .030 D 6.40 6.50 6.60 .252 .256 .260 E 6.30 6.40 6.50 .248 .252 .256 E1 4.30 4.40 4.50 .169 .173 .177 R 0.09 R1 0.09 b 0.19 b1 0.19 c c1 .006 .004 .004 0.30 .007 0.25 .007 0.09 0.20 .004 0.09 0.16 .004 0.22 1.0 REF e 15 NOM A1 θ1 SECTION A-A MIN 1.20 L1 b1 DIMENSION IN INCH MAX 12 REF θ3 12 REF .008 .006 .026 BSC 8 θ2 .010 .039 REF 0.65 BSC 0 .012 .009 0 8 12 REF 12 REF N 20 REF JEDEC M0-153 VARIATION AC Document No. 2113, Rev. I REVISION HISTORY Date 9/30/2003 Rev. E Reason Deleted WP from Functional Diagram, pg. 1 10/1/2003 F Changed designation to Advance 3/10/2004 G Added TSSOP package in all areas 3/25/2004 H Updated TSSOP package drawing 04/01/04 I Eliminated data sheet designation Update Features Update Description Update Pin Description Update device Operation Update Absolute Maximum Ratings Update Recommended Operating Conditions Update Potentiometer Characteristics Update Instructions Update Ordering Information Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ DPPs ™ AE2 ™ I2C is a trademark of Philips Corporation Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 2113 I 4/01/04