CAT5270

CAT5270 Dual Digitally Programmable Potentiometers (DPPt) with 256 Taps & I2C Compatible Interface Description http://onsemi.com The CAT5270 is a volatile 256−tap by two channels, digitally programmable potentiometer (DPP t) with an I2C compatible interface. Each DPP consists of a linear taper series of resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. On power up the wiper position goes to mid scale. The CAT5270 can be used as a potentiometer or as a two terminal, variable resistor. It is available in a 14−lead TSSOP package operating over the industrial temperature range (−40°C to 85°C). Features 1 TSSOP−14 Y SUFFIX CASE 948AM PIN CONNECTION A0 VCC RLO RHO RWO A2 SDA 1 A3 SCL GND RW1 RH1 RL1 A1 TSSOP−14 (Y) (Top View) • • • • • • • • • • Two Linear Taper Digitally Programmable Potentiometers 256 Resistor Taps per Potentiometer End to End Resistance 50 kW, 100 kW I2C Compatible Interface Low Wiper Resistance 75 W (typ.) 2.5 V to 5.5 V Operation Standby Current Less than 1 mA Power On to Mid Scale 14−lead TSSOP Package Industrial Temperature Range RH0 RH1 SDA SCL I2C COMPATIBLE INTERFACE 256−POSITION DECODE CONTROL ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. RW0 RW1 A0 A1 A2 A3 CONTROL LOGIC RL0 RL1 Figure 1. Functional Diagram © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 3 1 Publication Order Number: CAT5270/D CAT5270 Pin Description SCL: Serial Clock Table 1. PIN DESCRIPTION Pin # TSSOP−14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name A0 VCC RL0 RH0 RW0 A2 SDA A1 RL1 RH1 RW1 GND SCL A3 Function Device Address, LSB Supply Voltage Low Reference Terminal for Potentiometer 0 High Reference Terminal for Potentiometer 0 Wiper Terminal for Potentiometer 0 Device Address Serial Data Input/Output Device Address Low Reference Terminal for Potentiometer 1 High Reference Terminal for Potentiometer 1 Wiper Terminal for Potentiometer 1 Ground Bus Serial Clock Device Address The CAT5270 serial clock input pin is used to clock all data transfers into or out of the device. SDA: Serial Data The CAT5270 bidirectional serial data pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire−OR’d with the other open drain or open collector I/Os. A0, A1, A2, A3: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of sixteen devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5270. RH, RL: Resistor End Points The two sets of RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW: Wiper The RW pins are equivalent to the wiper terminal of a mechanical potentiometer. Device Operation The CAT5270 is two resistor arrays integrated with an I2C compatible interface and two 8−bit wiper control registers. Each resistor array contains 255 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control register via the I2C compatible interface. Also, the device can be instructed to operate in an “increment/ decrement” mode. http://onsemi.com 2 CAT5270 Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to VSS (Note 1) VCC with Respect to Ground Package Power Dissipation Capability (TA = 25°C) Lead Soldering Temperature (10 sec) Wiper Current Ratings −55 to +125 −65 to +150 −2.0 to +VCC + 2.0 −2.0 to +6.0 1.0 300 ±6 Units °C °C V V W °C mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns. Table 3. RECOMMENDED OPERATING CONDITIONS Parameters VCC Industrial Temperature Ratings +2.5 to +5.5 −40 to +85 Units V °C Table 4. POTENTIOMETER CHARACTERISTICS (VCC = +2.5 V to +5.5 V, unless otherwise specified.) Limits Symbol RPOT RPOT Parameter Potentiometer Resistance (100 kW) Potentiometer Resistance (50 kW) Potentiometer Resistance Tolerance RPOT Matching Power Rating IW RW RW VTERM Wiper Current Wiper Resistance Wiper Resistance Voltage on any RH or RL Pin Resolution Absolute Linearity (Note 4) Relative Linearity (Note 5) TCRPOT TCRATIO CH/CL/CW fc Temperature Coefficient of RPOT Ratiometric Temp. Coefficient Potentiometer Capacitances Frequency Response Rw(n)(actual) − R(n)(expected) (Note 7) Rw(n+1) – R[w(n)+LSB] (Note 7) (Note 3) (Note 3) (Note 3) RPOT = 50 kW (Note 3) 10/10/25 0.4 ±100 20 IW = ±3 mA @ VCC = 3 V IW = ±3 mA @ VCC = 5 V VSS = 0 V VSS 0.4 ±1 ±0.2 200 75 25°C, each pot Test Conditions Min Typ 100 50 ±20 1 50 ±3 300 150 VCC Max Units kW kW % % mW mA W W V % LSB (Note 6) LSB (Note 6) ppm/°C ppm/°C pF MHz 2. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC +1 V. 3. This parameter is tested initially and after a design or process change that affects the parameter. 4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 6. LSB = RTOT / 255 or (RH − RL) / 255, single pot 7. n = 0, 1, 2, ..., 255 http://onsemi.com 3 CAT5270 Table 5. D.C. OPERATING CHARACTERISTICS (VCC = +2.5 V to +5.5 V, unless otherwise specified.) Symbol ICC ISB ILI ILO VIL VIH VOL1 Parameter Power Supply Current Standby Current (VCC = 5.0 V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 2.5 V) IOL = 3 mA Test Conditions fSCL = 400 kHz, SDA = Open VCC = 5.5 V, Inputs = GND VIN = GND or VCC, SDA = Open VIN = GND to VCC VOUT = GND to VCC −1 VCC x 0.7 Min Max 1 5 10 10 VCC x 0.3 VCC + 1.0 0.4 Units mA mA mA mA V V V Table 6. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5 V) Symbol CI/O (Note 8) CIN (Note 8) Test Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, A3, SCL, WP) Conditions VI/O = 0 V VIN = 0 V Max 8 6 Units pF pF Table 7. A.C. CHARACTERISTICS 2.5 V – 5.5 V Symbol fSCL TI (Note 8) tAA tBUF (Note 8) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR (Note 8) tF (Note 8) tSU:STO tDH Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SLC Low to SDA Data Out and ACK Out Time the bus must be free before a new transmission can start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time 0.6 100 1.2 0.6 1.2 0.6 0.6 0 50 0.3 300 Parameter Min Max 400 200 1 Units kHz ns ms ms ms ms ms ms ns ns ms ns ms ns Table 8. POWER UP TIMING (Notes 8 and 9) Symbol tPUR tPUW Power−up to Read Operation Power−up to Write Operation Parameter Max 1 1 Units ms ms Table 9. WIPER TIMING Symbol tWRPO tWRL Parameter Wiper Response Time After Power Supply Stable Wiper Response Time After Instruction Issued Max 10 10 Units ms ms 8. This parameter is tested initially and after a design or process change that affects the parameter. 9. tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated. http://onsemi.com 4 CAT5270 tF tLOW SCL tHIGH tLOW tR tSU:STA SDA IN tHD:STA tHD:DAT tSU:DAT tSU:STO tAA SDA OUT tDH tBUF Figure 2. Bus Timing Serial Bus Protocol The following defines the features of the I2C compatible interface protocol: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5270 will be considered a slave device in all applications. START Condition After the Master sends a START condition and the slave address byte, the CAT5270 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. Slave Address Byte The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH (see Figure 3). The CAT5270 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition The most significant four bits of the slave address are a device type identifier. These bits for the CAT5270 are fixed at 0101[B] (refer to Figure 5). The next four bits, A3 − A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 − A0 input pins for the CAT5270 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 − A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Acknowledge A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition (see Figure 3). All operations must end with a STOP condition. Device Addressing The bus Master begins a transmission by sending a START condition. The Master then sends the Slave Addres Byte which contains the address of the particular slave device it is requesting. The four most significant bits of the 8−bit slave address are fixed as 0101 for the CAT5270. The next four significant bits (A3, A2, A1, A0) are the device address bits and define which device the Master is accessing (see Figure 5). Up to sixteen devices may be individually addressed by the system. Typically, +5 V (VCC) and ground are hard−wired to these pins to establish the device’s address. After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data (see Figure 4). The CAT5270 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8−bit byte. When the CAT5270 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5270 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. If the device has been selected with an IN/DEC operation it will no longer responds with acknoleadge as the received data it is not in a byte format. http://onsemi.com 5 CAT5270 SDA SCL START CONDITION STOP CONDITION Figure 3. Start/Stop Condition SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 4. Acknowledge Condition Device Type Identifier CAT5270 ID3 0 (MSB) ID2 1 ID1 0 ID0 1 A3 Slave Address A2 A1 A0 (LSB) Figure 5. Identification Format for Slave Address Byte http://onsemi.com 6 CAT5270 Instruction and Register Description Instruction Byte Increment/Decrement Command The next byte sent to the CAT5270 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I3 − I0. Instructions Instructions are three bytes in length. These instructions are: − Read Wiper Control Register – read the current wiper position of the selected potentiometer in the WCR − Write Wiper Control Register – change current wiper position in the WCR of the selected potentiometer − Increment/Decrement Wiper Control Register – change step by step the current wiper position in the WCR of the selected potentiometer The basic sequence of the three byte instructions is illustrated in Figure 8. Write Operation The last command is Increment/Decrement (Figures 9 and 10). The Increment/Decrement command is different from the other commands. Once the instruction is issued and the CAT5270 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instructions format for more details. Wiper Control Register (WCR) In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte that defines the requested operation of CAT5270. The instruction byte consists of a seven−bit opcode followed by pot/register selection bit. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the selected register. The CAT5270 acknowledges once more and the Master generates the STOP condition. The CAT5270 contains two 8−bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in two ways: it may be written by the host via Write Wiper Control Register instruction; or it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). P 0 1 WCR Set R0 wiper position Set R1 wiper position The Wiper Control Register is a volatile register that loses its contents when the CAT5270 is powered−down. Upon power−up, the wiper is set to midspan and may be repositioned anytime after the power has become stable. WCR Pot Selector Instruction Opcode I3 (MSB) I2 I1 I0 0 0 0 P0 (LSB) Figure 6. Instruction Byte Format Table 10. INSTRUCTION SET Instruction Set (Note 10) Instruction Read Wiper Control Register Write Wiper Control Register Increment/Decrement Wiper Control Register 10. 1/0 = data is one or zero I3 1 1 0 I2 0 0 0 I1 0 1 1 I0 1 0 0 F2 0 0 0 F1 0 0 0 F0 0 0 0 WCR/P 1/0 1/0 1/0 Operation Read the contents of the Wiper Control Register pointed to by P Write new value to the Wiper Control Register pointed to by P Enable Increment/decrement of the Control Latch pointed to by P http://onsemi.com 7 CAT5270 SDA 0 1 0 1 1 I3 0 I2 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 A C K WCR[7:0] S T O P S ID3I D2 ID1ID0 A3 A2 A1 A0 A T C A K Device ID Internal R T Address I1 I0 F2 F1 F0 P Instruction Opcode A C K Fixed Pot/WCR Figure 7. Write Instruction Sequence SDA 0 1 0 1 1 I3 0 I2 0 1 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 A C K Data Register D[7:0] S T O P S ID3I D2 ID1ID0 A3 A2 A1 A0 A T C A K Device ID Internal R T Address I1 I0 F2 F1 F0 P Instruction Opcode A C K Fixed Pot/WCR Figure 8. Read Instruction Sequence SDA 0 1 0 1 A2 A1 A0 A C K Internal Address 0 I3 0 I2 1 I1 0 0 0 0 I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P S ID3I D2 ID1ID0 A3 T A Device ID R T I0 F2 F1 F0 P Instruction Opcode A C K Fixed Pot/WCR Figure 9. Increment/Decrement Instruction Sequence INC/DEC Command Issued SCL No Fixed Length tWRL SDA RW Voltage Out Figure 10. Increment/Decrement Timing Limits Instruction Format Read Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 0 0 1 0 0 0 P A C K DATA 7 6 5 4 3 2 1 0 A C K S T O P Write Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 0 1 0 0 0 0 P A C K DATA 7 6 5 4 3 2 1 0 A C K S T O P Increment (I)/Decrement (D) Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 0 0 1 0 0 0 0 P A C K DATA I / D I / D .. . I / D I / D S T O P http://onsemi.com 8 CAT5270 PACKAGE DIMENSIONS TSSOP14, 4.4x5 CASE 948AM−01 ISSUE O b SYMBOL A A1 A2 b c E1 E D E E1 e L L1 MIN 0.05 0.85 0.19 0.13 4.90 6.30 4.30 NOM MAX 1.10 0.15 0.95 0.30 0.20 5.10 6.50 4.50 0.65 BSC 1.00 REF 0.45 0.75 θ PIN#1 IDENTIFICATION TOP VIEW D e 0º 8º A2 A θ1 A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. END VIEW L L1 http://onsemi.com 9 CAT5270 Example of Ordering Information (Notes 11 and 12) Prefix CAT Device # 5270 Suffix Y I − 00 −G T2 Company ID Product Number 5270 Package Y: TSSOP Temperature Range I = Industrial (−40°C to +85°C) Lead Finish G: NiPdAu Tape & Reel (Note 13) T: Tape & Reel 2: 2,000 Units / Reel Resistance 50: 50 kW 00: 100 kW ORDERING INFORMATION Part Number CAT5270YI−50−GT2 CAT5270YI−00−GT2 Resistance 50 kW 100 kW Package TSSOP−14 Lead Finish NiPdAu 11. All packages are RoHS−compliant (Lead−free, Halogen−free). 12. The device used in the following example: CAT5270YI−00−GT2 is a TSSOP, Industrial Temperature, 100 kW, NiPdAu (TSSOP−14), Tape & Reel, 2,000/Reel. 13. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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