CAT5271 Dual 256-Position I2C Compatible Digital Potentiometer
The CAT5271 is a dual 256−position digitally programmable linear taper potentiometer ideally suited for replacing mechanical potentiometers and variable resistors. The wiper settings are controlled through an I2C−compatible digital interface. Upon power−up, the wiper assumes a midscale position and may be repositioned anytime after the power is stable. The device can be programmed to go to a shutdown state during operation. The CAT5271 operates from 2.7 V to 5.5 V, while consuming less than 2 mA. This low operating current, combined with a small package footprint, makes the CAT5271 ideal for battery−powered portable applications. The CAT5271, designed as a pin for pin replacement for the AD5243, is offered in the 10−lead MSOP package and operates over the −40°C to +85°C industrial temperature range.
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MSOP−10 R, Z SUFFIX CASE 846AE
MARKING DIAGRAM
• • • • • • • • •
Dual 256−position End−to−End Resistance: 50 kW, 100 kW I2C Compatible Interface Power−on Preset to Midscale Single Supply 2.7 V to 5.5 V Low Temperature Coefficient 100 ppm/°C Low Power, IDD 2 mA max Wide Operating Temperature −40°C to +85°C RoHS−compliant MSOP−10 Package (3 mm x 4.9 mm)
ANCC YMR 1 1
ANCE YMR
Typical Applications
ANCC = 50 kW ANCE = 100 kW Y = Production Year Y = (Last Digit) M = Production Month M = (1 − 9, A, B, C) R = Revision
• Potentiometer Replacement • Transducer Adjustment of Pressure, Temperature, Position, • •
Chemical, and Optical Sensors RF Amplifier Biasing Gain Control and Offset Adjustment
B1 A1 W2 GND VDD
PIN CONNECTIONS
1 W1 B2 A2 SDA SCL (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
September, 2009 − Rev. 1
1
Publication Order Number: CAT5271/D
CAT5271
VCC
Wiper Control Register 1 I2C Interface
A1 W1 B1
SCL SDA
Wiper Control Register 2
A2 W2 B2
GND
Figure 1. Functional Block Diagram Table 1. ORDERING INFORMATION
Part Number CAT5271ZI−50−GT3 CAT5271ZI−00−GT3 Resistance 50 kW 100 kW Temperature Range −40°C to 85°C Package MSOP−10 (Pb−Free) Shipping† 3000/Tape & Reel 3000/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Table 2. PIN FUNCTION DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 Pin Name B1 A1 W2 GND VDD SCL SDA A2 B2 W1 B1 Terminal A1 Terminal W2 Terminal Digital Ground Positive Power Supply Serial Clock Input Serial Data Input / Output A2 Terminal B2 Terminal W1 Terminal Description
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1)
Rating VDD to GND A1, B1, W1, A2, B2, W2 Voltage to GND IMAX Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Value −0.3 to 6.5 VDD ±20 0 to 6.5 −40 to +85 150 −65 to +150 300 mA V °C °C °C °C Unit V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance.
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Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions
VDD = 2.7 V to 5.5 V; VA = VDD; VB = 0 V; –40°C < TA < +85°C; unless otherwise noted. (Note 2) Parameter DC CHARACTERISTICS — RHEOSTAT MODE Resistor Differential Nonlinearity (Note 4) Resistor Integral Nonlinearity (Note 4) Nominal Resistor Tolerance (Note 5) Resistance Temperature Coefficient Wiper Resistance RWB, VA = no connection RWB, VA = no connection TA = 25°C VAB = VDD, Wiper = no connection VDD = 5 V, IW = ±3 mA VDD = 3 V, IW = ±3 mA DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity (Note 6) Integral Nonlinearity (Note 6) Voltage Divider Temperature Coefficient Full−Scale Error Zero−Scale Error RESISTOR TERMINALS Voltage Range (Note 7) Capacitance (Note 8) A, B Capacitance (Note 8) W Common−Mode Leakage (Note 8) DIGITAL INPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current POWER SUPPLIES Power Supply Range Supply Current Power Dissipation (Note 8) Power Supply Sensitivity Bandwidth –3 dB Total Harmonic Distortion VW Settling Time (50 kW/100 kW) VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V nVDD = +5 V ±10%, Code = Midscale RAB = 50 kW / 100 kW, Code = 0x80 VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kW VA = 5 V, VB = 0 V, ±1 LSB error band VDD RANGE IDD PDISS PSS BW THDW tS 100/40 0.05 2 2.7 0.3 5.5 2 0.2 ±0.05 V mA mW %/% kHz % ms VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V VIH VIL VIH VIL IIL 0.7 x VDD 0.3VDD ±1 0.7 x VDD 0.3VDD V V V V mA f = 1 MHz, measured to GND, Code = 0 x 80 f = 1 MHz, measured to GND, Code = 0 x 80 VA = VB = VDD/2 VA,B,W CA,B CW ICM GND 45 60 1 VDD V pF pF nA Code = 0x80 Code = 0xFF Code = 0x00 N DNL INL nVW/nT VWFSE VWZSE −3 0 −1 −1 ±0.1 ±0.4 100 −1 1 0 3 8 +1 +1 Bits LSB LSB ppm/°C LSB LSB R−DNL R−INL nRAB nRAB/nT RW −1 −2 −20 100 50 100 120 250 ±0.1 ±0.4 +1 +2 +20 LSB LSB % ppm/°C W Test Conditions Symbol Min Typ (Note 3) Max Unit
DYNAMIC CHARACTERISTICS (Notes 8 and 10)
2. VA applies to both A1 and A2, VB applies to both B1 and B2. 3. Typical specifications represent average readings at +25°C and VDD = 5 V. 4. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 5. VAB = VDD, Wiper (VW) = no connect. 6. INL and DNL are measured at VW with the digital potentiometer configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 7. Resistor terminals A, B, W have no limitations on polarity with respect to each other. 8. Guaranteed by design and not subject to production test. 9. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 10. All dynamic characteristics use VDD = 5 V.
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Table 5. CAPACITANCE
TA = 25°C, f = 1.0 MHz, VDD = 5 V Symbol CI/O (Note 11) Test Input/Output Capacitance (SDA, SCL) Conditions VI/O = 0V Max 8 Units pF
Table 6. POWER UP TIMING (Notes 11 and 12)
Symbol tPUR tPUW Power−up to Read Operation Power−up to Write Operation Parameter Max 1 1 Units ms ms
11. This parameter is tested initially and after a design or process change that affects the parameter. 12. tPUR and t PUW are delays required from the time VCC is stable until the specified operation can be initiated.
Table 7. DIGITAL POTENTIOMETER TIMING
Symbol tWRPO tWR Parameter Wiper Response Time After Power Supply Stable Wiper Response Time: SCL falling edge after last bit of wiper position data byte to wiper change Min Max 50 20 Units ms ms
Table 8. A.C. CHARACTERISTICS
VDD = +2.7 V to +5.5 V, −40°C to +85°C unless otherwise specified. Symbol fSCL tHIGH tLOW tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF tR tF tDH TI tAA Clock Frequency Clock High Period Clock Low Period Start Condition Setup Time (for a Repeated Start Condition) Start Condition Hold Time Data in Setup Time Data in Hold Time Stop Condition Setup Time Time the bus must be free before a new transmission can start SDA and SCL Rise Time SDA and SCL Fall Time Data Out Hold Time Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out 100 50 1 600 1300 600 600 100 0 600 1300 300 300 Parameter Min Typ Max 400 Units kHz ns ns ns ns ns ns ns ns ns ns ns ns ms
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TYPICAL CHARACTERISTICS
0.03 0.02 0.01 0 ERROR (LSB) ERROR (LSB) −0.1 −0.2 −0.3 −0.4 −0.5 INL DNL 0.1 0
−0.01 −0.02 −0.03 −0.04 −0.05 0 32 64 96 128 TAP 160 192 224 256
0
32
64
96
128 TAP
160
192
224 256
Figure 2. Differential Non−Linearity, VDD = 5.6 V
120 100 VDD = 2.6 V 80 Rw (W) 60 3.3 V 40 20 0 4.0 V 0 50 100 TAP 5.6 V Vw (V) 4 3 2 1 0 6
Figure 3. Integral Non−Linearity, VDD = 5.6 V
5.6 V 5 5.0 V 4.0 V 3.3 V VDD = 2.6 V
150
200
250
0
52
104 TAP
156
208
260
Figure 4. Wiper Resistance at Room Temperature
400 350 300 ISB (nA)
Figure 5. Wiper Voltage
T = 90°C T = −45°C
250 200 150 100 T = 25°C
2
3
4 VDD (V)
5
6
Figure 6. Standby Current
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TYPICAL CHARACTERISTICS
0.4 102.15 102.10 102.05 0.2 R (kW) 0 −0.2 −50 −20 10 40 70 100 D (%) 102.00 101.95 101.90 101.85 101.80 101.75 −50 −20 10 40 70 100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Change in End−to−End Resistance
Figure 8. End−to−End Resistance vs. Temperature
30 25
0 −6 VDD = 5 V PSRR (dB) −12 A (dB) −18 −24 −30 −36 VDD = 3 V
20 VDD = 5 V 15 10 5 0 VDD = 3 V
1
10 f (KHz)
100
1000
1
10 f (KHz)
100
1000
Figure 9. Gain vs. Bandwidth (Tap 0x80)
Figure 10. PSRR
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Basic Operation The CAT5271 is a dual 256−position digitally controlled potentiometer. When power is first applied, the wipers assume a mid−scale position. Once the power supply is stable, the wipers may be repositioned via the I2C compatible interface. Programming: Variable Resistor
Rheostat Mode
The equation for determining the digitally programmed output resistance between W and B is
R WB + D R AB ) R W 256
(eq. 1)
The resistance between terminals A and B, RAB, has a nominal value of 50 kW or 100 kW and has 256 contact points accessed by the wiper terminal, plus the B terminal contact. Data in the 8−bit Wiper register is decoded to select one of these 256 possible settings. The wiper’s first connection is at the B terminal, corresponding to control position 0x00. Ideally this would present a 0 W between the Wiper and B, but just as with a mechanical rheostat there is a small amount of contact resistance to be considered, there is a wiper resistance comprised of the RON of the FET switch connecting the wiper output with its respective contact point. In CAT5271 this ‘contact’ resistance is typically 50 W. Thus a connection setting of 0x00 yields a minimum resistance of 50 W between terminals W and B. For a 100 kW device, the second connection, or the first tap point, corresponds to 441 W (RWB = RAB/256 + RW = 390.6 + 50 W) for data 0x01. The third connection is the next tap point, is 831 W (2 x 390.6 + 50 W) for data 0x02, and so on. Figure 11 shows a simplified equivalent circuit where the last resistor string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance.
A RS
where D is the decimal equivalent of the binary code loaded in the 8−bit Wiper register, RAB is the end−to−end resistance, and RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 100 kW and the A terminal is open circuited, the following output resistance RWB will be set for the indicated Wiper register codes:
Table 9. CODES AND CORRESPONDING RWB RESISTANCE FOR RAB = 100 kW, VDD = 5 V
D (Dec.) 255 128 1 0 RWB (W) 99,559 50,050 441 50 Midscale 1 LSB Zero Scale (Wiper Contact Resistance) Output State Full Scale (RAB – 1 LSB + RW)
Be aware that in the zero−scale position, the wiper resistance of 50 W is still present. Current flow between W and B in this condition should be limited to a maximum pulsed current of no more than 20 mA. Failure to heed this restriction can cause degradation or possible destruction of the internal switch contact. Similar to the mechanical potentiometer, the resistance of the DPP (Digitally Programmed Potentiometer) between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is
R WA(D) + 256 * D R AB ) R W 256
(eq. 2)
RS Wiper Register and Decoder
RS W
For RAB = 100 kW and the B terminal open circuited, the following output resistance RWA will be set for the indicated Wiper register codes.
Table 10. CODES AND CORRESPONDING RWA RESISTANCE FOR RAB = 100 kW, VDD = 5 V
D (Dec.) 255 RWA (W) 441 50,050 99,659 100,050 Full Scale Midscale 1 LSB Zero Scale Output State
RS
B
128 1
Figure 11. CAT5271 Equivalent DPP Circuit
0
Typical device to device resistance matching is lot dependent and may vary by up to ±20%.
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CAT5271
ESD Protection
Digital Input LOGIC
Power−up Sequence
GND
Because ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 12), it is recommended that VDD/GND be powered before applying any voltage to terminals A, B, and W. The ideal power−up sequence is: GND, VDD, digital inputs, and then VA/B/W. The order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND.
Power Supply Bypassing
W, A, B Potentiometer
GND
Good design practice employs compact, minimum lead length layout design. Leads should be as direct as possible. It is also recommended to bypass the power supplies with quality low ESR Ceramic chip capacitors of 0.01 mF to 0.1 mF. Low ESR 1 mF to 10 mF tantalum or electrolytic capacitors can also be applied at the supplies to suppress transient disturbances and low frequency ripple. As a further precaution digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce.
VDD C3 10 mF + C1 0.1 mF VDD CAT5271 GND
Figure 12. ESD Protection Networks Terminal Voltage Operating Range
The CAT5271 VDD and GND power supply define the limits for proper 3−terminal digital potentiometer operation. Signals or potentials applied to terminals A, B or the wiper must remain inside the span of VDD and GND. Signals which attempt to go outside these boundaries will be clamped by the internal forward biased diodes.
VDD
Figure 14. Power Supply Bypassing
W, A, B CAT5271 LOGIC
GND
Figure 13.
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CAT5271
The following defines the features of the I2C bus protocol: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5271 will be considered a slave device in all applications.
START Condition
I2C Bus Protocol
is logic high, then a Read instruction is performed. If the bit is logic low, then the Write command is executed. After the Master sends a START condition and the slave address byte, the CAT5271 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address.
Acknowledge
The START condition precedes all commands to the device, and is defined as a high to low transition of SDA when SCL is high. The CAT5271 monitors the SDA and SCL lines and will not respond until this condition is met.
STOP Condition
A low to high transition of SDA when SCL is high determines the STOP condition. All operations must end with a STOP condition.
Device Addressing
After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT5271 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8−bit byte. When the CAT5271 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5271 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. Write Operation In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the wiper register. The CAT5271 acknowledges once more and the Master generates the STOP condition.
tR tLOW
The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The seven most significant bits of the 8−bit slave address are fixed as 0101111 for the CAT5271. The next bit (R/W) selects between the type of the instruction Read or Write. If the bit
tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tHD:STA tHD:DAT tHIGH
tSU:DAT
tSU:STO
tDH
tBUF
Figure 15. Bus Timing Diagram
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SDA
SCL START CONDITION
Figure 16. Start/Stop Condition
STOP CONDITION
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START
Figure 17. Acknowledge Condition
ACKNOWLEDGE
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INSTRUCTION AND REGISTER DESCRIPTION
SLAVE ADDRESS BYTE
The remainder of the bits in the instruction byte are don’t care bits.
Read Operation
The first byte sent to the CAT5271 from the master/processor is called the Slave Address Byte. The most significant seven bits of the slave address are a device type identifier. For the CAT5271, these bits are fixed at 0101111. The following bit (R/W) selects between a Read or a Write operation. If the bit is logic high, then a Read instruction is performed. If the bit is low, then the Write command is executed.
INSTRUCTION BYTE
Write and Read instructions are respectively three and two bytes in length. The basic sequence of the two instructions is illustrated in Table 11 and 12.
Write Operation
In the write instruction, the second byte first bit (A0) selects between the potentiometer 1 and 2: a logic low is for the potentiometer 1, and a logic high is for potentiometer 2. The following bit (SD) is the shutdown bit. A logic high causes an open circuit at terminal A while shorting the wiper terminal W to terminal B. The “shutdown” operation does not change the contents of the wiper register. When the shutdown bit, SD, goes back to a logic low, the previous wiper position is restored. Also during shutdown, new settings can be programmed. As soon as the device is returned from shutdown, the wiper position is set according to the wiper register value.
Table 11. Write
S 0 1 0 1 1 1 1 W A A0 SD X X X X X
In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences. There is no potentiometer channel selection bit in the Read command. The addressed channel is the one that is previously selected in the write mode. If it desired to read the potentiometer wiper register values of both channels, the first potentiometer must be addressed in write mode and then change to read mode to read the first channel value. After that, the user must return the device to write mode with the second potentiometer selected and read the second potentiometer wiper register value in read mode. It is not necessary for users to issue the third data byte in write mode for subsequent read operation.
Wiper Control
The CAT5271 contains two 8−bit Wiper Control Register (WCR). The Wiper Control Register output is decoded to select one of 256 switches along its resistor array. The contents of the WCR may be written by the host via Write instruction. The Wiper Control Registers are a volatile register that loses its contents when the CAT5271 is powered−down. Upon power−up, the wiper is set to midscale and may be repositioned anytime after the power has become stable.
X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte SDA 0 S T A R T 10 11 1 1 R/W A C K Slave Address Byte A0
Instruction Byte
Data Byte
SD
XX
X
X
XX A C K
D7
D6
D5
D4
D3
D2
D1
D0 AS CT KO P
Instruction Byte
Data Byte
Table 12. READ
S 0 1 0 1 1 1 1 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte SDA S T A R T 0 1 0 1 1 1 1 R/W A C K Slave Address Byte D7 D6 D5
Data Byte D4 D3 D2 D1 D0 N A C K S T O P
Data Byte
Legend
S= P= A= D= R= W=
Start Stop Acknowledge Data bit Read (bit is 1 for Read instruction) Write (bit is 0 for Write instruction)
A0 = Potentiometer Channel (1 or 2) Select Bit SD = Shut Down: 0: normal operation 1: wiper is parked at B terminal and terminal A is open circuit. X = Don’t Care
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PACKAGE DIMENSIONS
MSOP 10, 3x3 CASE 846AE−01 ISSUE O
SYMBOL A A1 A2 b c E E1 D E E1 e L L1 L2
MIN
NOM
MAX 1.10
0.00 0.75 0.17 0.13 2.90 4.75 2.90 0.40
0.05 0.85
0.15 0.95 0.27 0.23
3.00 4.90 3.00 0.50 BSC 0.60 0.95 REF 0.25 BSC
3.10 5.05 3.10 0.80
θ
TOP VIEW
0º
8º
DETAIL A D
A
A2
A1
e SIDE VIEW
b
c END VIEW
q L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A
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CAT5271/D
