CAT6095VP2GI-T4

CAT6095 Digital Output Temperature Sensor Description The CAT6095 is a JEDEC JC42.4 compliant Temperature Sensor designed for general purpose temperature measurements requiring a digital output. The CAT6095 measures temperature at least 10 times every second. Temperature readings can be retrieved by the host via the serial interface, and are compared to high, low and critical trigger limits stored into internal registers. Over or under limit conditions can be signaled on the open−drain EVENT pin. The CAT6095 is packaged in space saving TDFN package with exposed backside die attach pads (DAP). The exposed DAP reduces overall thermal resistance, thus providing faster response to thermal changes when compared to SOIC, TSSOP or SOT packages. http://onsemi.com TDFN−8 VP2 SUFFIX CASE 511AK PIN CONFIGURATION A0 Features • • • • • • • • JEDEC JC42.4 Compliant Temperature Sensor Temperature Range: −40°C to +125°C Supply Range: 3.3 V ± 10% I2C / SMBus Interface Schmitt Triggers and Noise Suppression Filters on SCL and SDA Inputs Low Power CMOS Technology 2 x 3 x 0.75 mm TDFN Package These Devices are Pb−Free and are RoHS Compliant CAT6095 A2, A1, A0 EVENT A2 SCL VSS SDA (Top View) For the location of Pin 1, please consult the corresponding package drawing. MARKING DIAGRAM HMC ALL YM G HMC A LL Y M G EVENT VCC A1 VCC SCL 1 = Specific Device Code = Assembly Location Code = Assembly Lot Number (Last Two Digits) = Production Year (Last Digit) = Production Month (1 − 9, O, N, D) = Pb−Free Package PIN FUNCTIONS SDA Pin Name A0, A1, A2 VSS Figure 1. Functional Symbol Function Device Address Input SDA Serial Data Input/Output SCL Serial Clock Input EVENT Open−drain Event Output VCC Power Supply VSS Ground DAP Backside Exposed DAP at VSS ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. © Semiconductor Components Industries, LLC, 2011 May, 2011 − Rev. 5 1 Publication Order Number: CAT6095/D CAT6095 Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Operating Temperature −45 to +130 °C Storage Temperature −65 to +150 °C Voltage on any pin with respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. The A0 pin can be raised to a HV level compatible with the use of a DDR3 SPD device sharing the bus with the TS. SCL and SDA inputs can be raised to the maximum limit, irrespective of VCC. Table 2. TEMPERATURE CHARACTERISTICS (VCC = 3.3 V ± 10%, TA = −40°C to +125°C, unless otherwise specified) Parameter Temperature Reading Error Class B, JC42.4 compliant Test Conditions/Comments Max Unit +75°C ≤ TA ≤ +95°C, active range ±1.0 °C +40°C ≤ TA ≤ +125°C, monitor range ±2.0 °C −20°C ≤ TA ≤ +125°C, sensing range ±3.0 °C 12 Bits 0.0625 °C 100 ms 92 °C/W ADC Resolution Temperature Resolution Temperature Conversion Time Thermal Resistance (Note 2) qJA Junction−to−Ambient (Still Air) 2. Power Dissipation is defined as PJ = (TJ − TA)/qJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal resistance value refers to the case of a package being used on a standard 2−layer PCB. Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 3.3 V ± 10%, TA = −40°C to +125°C, unless otherwise specified) Symbol ICC Parameter Supply Current ISHDN IL I/O Pin Leakage Current Test Conditions/Comments Min Max Unit TS active 200 mA TS shut−down; no bus activity 10 mA 2 mA VIL Input Low Voltage Pin at GND or VCC −0.5 0.3 x VCC V VIH Input High Voltage 0.7 x VCC VCC + 0.5 V VOL Output Low Voltage 0.4 V IOL = 3 mA, VCC > 2.5 V http://onsemi.com 2 CAT6095 Table 4. A.C. CHARACTERISTICS (VCC = 3.3 V ± 10%, TA = −40°C to +125°C) (Note 3) Symbol Min Max Units Clock Frequency 10 400 kHz tHIGH High Period of SCL Clock 600 ns tLOW Low Period of SCL Clock 1300 ns FSCL (Note 4) tTIMEOUT (Note 4) Parameter 35 ms tR (Note 5) SMBus SCL Clock Low Timeout SDA and SCL Rise Time 300 ns tF (Note 5) SDA and SCL Fall Time 300 ns tSU:DAT (Note 6) Data Setup Time tHD:DAT (Note 5) Data Hold Time (for Input Data) 25 100 ns 0 ns Data Hold Time (for Output Data) 300 900 ns tSU:STA START Condition Setup Time 600 ns tHD:STA START Condition Hold Time 600 ns tSU:STO STOP Condition Setup Time 600 ns tBUF Bus Free Time Between STOP and START 1300 ns Ti Noise Pulse Filtered at SCL and SDA Inputs 100 ns Power−up Delay to Valid Temperature Recording 100 ms tPU (Note 7) 3. Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 11. Bus loading must be such as to allow meeting the VIL, VOL as well as the various timing limits. 4. The TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time−out count is started (and then re−started) on every negative transition of SCL in the time interval between START and STOP. 5. In a “Wired−OR” system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be able to sink the (external) bus pull−up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster than SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW − tHD:DAT − tSU:DAT, where tLOW and tHD:DAT are actual values (rather than spec limits). A shorter tHD:DAT leaves more room for a longer SDA tR, allowing for a more capacitive bus or a larger bus pull−up resistor. At the minimum tLOW spec limit of 1300 ns, the maximum tHD:DAT of 900 ns demands a maximum SDA tR of 300 ns. The CAT6095’s maximum tHD:DAT is