CAT93C46

CAT93C46 1 kb Microwire Serial EEPROM Description The CAT93C46 is a 1 kb Serial EEPROM memory device which is configured as either 64 registers of 16 bits (ORG pin at VCC) or 128 registers of 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C46 features a self−timed internal write with auto−clear. On−chip Power−On Reset circuit protects the internal logic against powering up in the wrong state. Features http://onsemi.com • • • • • • • • • • • • High Speed Operation: 2 MHz 1.8 V to 5.5 V Supply Voltage Range Selectable x8 or x16 Memory Organization Self−Timed Write Cycle with Auto−Clear Software Write Protection Power−up Inadvertant Write Protection Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial Temperature Ranges 8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant* VCC PDIP−8 L SUFFIX CASE 646AA TSSOP−8 Y SUFFIX CASE 948AL SOIC−8 V, W SUFFIX CASE 751BD SOIC−8 X SUFFIX CASE 751BE TDFN−8 VP2 SUFFIX CASE 511AK PIN CONFIGURATIONS CS SK DI DO 1 VCC NC NC VCC ORG CS SK GND 1 ORG GND DO DI PDIP (L), SOIC (V, X), TSSOP (Y), TDFN (VP2) (Top View) SOIC (W) (Top View) ORG CS SK DI CAT93C46 DO PIN FUNCTION Pin Name CS SK DI GND DO VCC GND ORG Function Chip Select Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization No Connection Figure 1. Functional Symbol *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. NC Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 6 1 Publication Order Number: CAT93C46/D CAT93C46 Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Voltage on Any Pin with Respect to Ground (Note 1) Value −65 to +150 −0.5 to +6.5 Units °C V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol NEND (Note 3) TDR Endurance Data Retention Parameter Min 1,000,000 100 Units Program / Erase Cycles Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Block Mode, VCC = 5 V, 25°C Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = −40°C to +85°C, unless otherwise specified.) Symbol ICC1 ICC2 ISB1 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Test Conditions fSK = 1 MHz VCC = 5.0 V fSK = 1 MHz VCC = 5.0 V VIN = GND or VCC, CS = GND ORG = GND VIN = GND or VCC, CS = GND ORG = Float or VCC VIN = GND to VCC VOUT = GND to VCC, CS = GND 4.5 V v VCC < 5.5 V 4.5 V v VCC < 5.5 V 1.8 V v VCC < 4.5 V 1.8 V v VCC < 4.5 V 4.5 V v VCC < 5.5 V IOL = 2.1 mA 4.5 V v VCC < 5.5 V IOH = −400 mA 1.8 V v VCC < 4.5 V IOL = 1 mA 1.8 V v VCC < 4.5 V IOH = −100 mA VCC − 0.2 2.4 0.2 −0.1 2 0 VCC x 0.7 Min Max 1 500 2 Units mA mA mA ISB2 Power Supply Current (Standby) (x16Mode) 1 mA ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage 1 1 0.8 VCC + 1 VCC x 0.2 VCC + 1 0.4 mA mA V V V V V V V V http://onsemi.com 2 CAT93C46 Table 4. PIN CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5 V) Symbol COUT (Note 4) CIN (Note 4) Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Conditions VOUT = 0 V VIN = 0 V Min Typ Max 5 5 Units pF pF 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. Table 5. A.C. CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = −40°C to +85°C, unless otherwise specified.) (Note 5) Limits Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ (Note 6) tEW tCSMIN tSKHI tSKLOW tSV SKMAX CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High−Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 0.25 0.25 0.25 0.25 2000 Parameter Min 50 0 100 100 0.25 0.25 100 5 Max Units ns ns ns ns ms ms ns ms ms ms ms ms kHz 5. Test conditions according to “AC Test Conditions” table. 6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. Table 6. POWER−UP TIMING (Notes 7 and 8) Symbol tPUR tPUW Power−up to Read Operation Power−up to Write Operation Parameter Max 1 1 Units ms ms 7. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 8. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Table 7. A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages Output Load v 50 ns 0.4 V to 2.4 V 0.8 V, 2.0 V 0.2 VCC to 0.7 VCC 0.5 VCC 4.5 V v VCC v 5.5 V 4.5 V v VCC v 5.5 V 1.8 V v VCC v 4.5 V 1.8 V v VCC v 4.5 V Current Source IOLmax/IOHmax; CL = 100 pF http://onsemi.com 3 CAT93C46 Device Operation The CAT93C46 is a 1024−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C46 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9−bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 10−bit instructions control the reading, writing and erase operations of the device. The CAT93C46 operates on a single power supply and will generate on chip the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status during a write operation. The serial communication protocol follows the timing shown in Figure 2. The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O Table 8. INSTRUCTION SET Address Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Start Bit 1 1 1 1 1 1 1 Opcode 10 11 01 00 00 00 00 x8 A6−A0 A6−A0 A6−A0 11XXXXX 00XXXXX 10XXXXX 01XXXXX x16 A5−A0 A5−A0 A5−A0 11XXXX 00XXXX 10XXXX 01XXXX D7−D0 D15−D0 D7−D0 D15−D0 x8 Data x16 Comments Read Address AN–A0 Clear Address AN–A0 Write Address AN–A0 Write Enable Write Disable Clear All Addresses Write All Addresses pin. The Ready/Busy flag can be disabled only in Ready state; no change is allowed in Busy state. The format for all instructions sent to the device is a logical “1” start bit, a 2−bit (or 4−bit) opcode, 6−bit address (an additional bit when organized X8) and for write operations a 16−bit data field (8−bit for X8 organization). Read Upon receiving a READ command (Figure 3) and an address (clocked into the DI pin), the DO pin of the CAT93C46 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). Erase/Write Enable and Disable The CAT93C46 powers up in the write disable state. Any writing after power−up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C46 write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. The EWEN and EWDS instructions timing is shown in Figure 4. http://onsemi.com 4 CAT93C46 tSKHI SK tDIS DI tCSS CS tDIS DO tPD0, tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH Figure 2. Synchronous Data Timing SK tCSMIN CS AN DI 1 1 0 tHZ 0 DN DN−1 D1 D0 HIGH−Z AN−1 A0 STANDBY DO HIGH−Z tPD0 Figure 3. Read Instruction Timing SK CS STANDBY DI 1 0 0 * * ENABLE = 11 DISABLE = 00 Figure 4. EWEN/EWDS Instruction Timing http://onsemi.com 5 CAT93C46 Write Erase All After receiving a WRITE command (Figure 5), address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking for auto−clear and data store cycles on the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. Since this device features Auto−Clear before write, it is NOT necessary to erase a memory location before it is written into. Erase Upon receiving an ERAL command (Figure 7), the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Write All Upon receiving an ERASE command and address, the CS (Chip Select) pin must be de−asserted for a minimum of tCSMIN (Figure 6). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. SK Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN (Figure 8). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. tCSMIN CS AN DI 1 0 1 tSV DO HIGH−Z BUSY READY tEW tHZ HIGH−Z AN−1 A0 DN D0 STATUS VERIFY STANDBY Figure 5. Write Instruction Timing http://onsemi.com 6 CAT93C46 SK CS AN DI 1 1 1 tSV DO HIGH−Z AN−1 A0 STATUS VERIFY tCS MIN STANDBY tHZ BUSY tEW READY HIGH−Z Figure 6. Erase Instruction Timing SK CS STATUS VERIFY tCS MIN STANDBY DI 1 0 0 1 0 tSV tHZ BUSY tEW READY HIGH−Z DO HIGH−Z Figure 7. ERAL Instruction Timing SK CS STATUS VERIFY tCSMIN STANDBY DI 1 0 0 0 1 DN D0 tSV tHZ BUSY tEW READY HIGH−Z DO Figure 8. WRAL Instruction Timing http://onsemi.com 7 CAT93C46 PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL A A1 A2 b E1 b2 c D E E1 e eB PIN # 1 IDENTIFICATION D L 7.87 2.92 3.30 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 BSC 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25 7.11 MIN NOM MAX 5.33 TOP VIEW E A A2 A1 b2 L c e SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. b eB END VIEW http://onsemi.com 8 CAT93C46 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL A A1 b c E1 E D E E1 e h L PIN # 1 IDENTIFICATION TOP VIEW 0.25 0.40 MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.50 1.27 NOM MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00 θ 0º 8º D h A1 A θ c e SIDE VIEW b L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 9 CAT93C46 PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL A A1 b c E1 E D E E1 e L MIN NOM MAX 2.03 0.05 0.36 0.19 5.13 7.75 5.13 1.27 BSC 0.51 0.25 0.48 0.25 5.33 8.26 5.38 0.76 θ PIN#1 IDENTIFICATION TOP VIEW 0º 8º D A q e b A1 L c END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. http://onsemi.com 10 CAT93C46 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL A A1 A2 b E1 E c D E E1 e L L1 MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 NOM MAX 1.20 0.15 0.90 1.05 0.30 0.20 3.00 6.40 4.40 0.65 BSC 1.00 REF 3.10 6.50 4.50 0.50 0.60 0.75 θ e 0º 8º TOP VIEW D A2 A q1 c A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. L1 END VIEW L http://onsemi.com 11 CAT93C46 PACKAGE DIMENSIONS TDFN8, 2x3 CASE 511AK−01 ISSUE A D A e b E E2 PIN#1 IDENTIFICATION A1 PIN#1 INDEX AREA D2 L TOP VIEW SIDE VIEW BOTTOM VIEW SYMBOL A A1 A2 A3 b D D2 E E2 e L MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20 NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30 MAX 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40 FRONT VIEW A2 A3 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229. http://onsemi.com 12 CAT93C46 Example of Ordering Information Prefix CAT Device # 93C46 Suffix V I −G T3 Company ID Product Number 93C46 Temperature Range I = Industrial (−40°C to +85°C) Lead Finish G: NiPdAu Blank: Matte−Tin Tape & Reel (Note 14) T: Tape & Reel 2: 2,000 Units / Reel (Note 12) 3: 3,000 Units / Reel Package L: PDIP V: SOIC, JEDEC W: SOIC, JEDEC X: SOIC, EIAJ Y: TSSOP VP2: TDFN (2 x 3 mm) 9. All packages are RoHS−compliant (Lead−free, Halogen−free). 10. The standard lead finish for the SOIC, EIAJ (X) package is Matte−Tin; the standard lead finish for all other packages is NiPdAu. 11. The device used in the above example is a CAT93C46VI−GT3 (SOIC, JEDEC, Industrial Temperature, NiPdAu, Tape & Reel). 12. The SOIC, EIAJ (X) package is available in reels of 2,000 pcs/reel (i.e. CAT93C46XI−T2). All other packages are offered in reels of 3,000 pcs/reel. 13. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 14. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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