CAT93C46YI

CAT93C46 1K-Bit Microwire Serial EEPROM FEATURES DESCRIPTION ■ High speed operation: 1MHz The CAT93C46 is a 1K-bit Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C46 is manufactured using Catalyst’s advanced CMOS EEPROM floating gate technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and 8-pad TDFN packages. ■ Low power CMOS technology ■ 1.8 to 5.5 volt operation ■ Selectable x8 or x16 memory organization ■ Self-timed write cycle with auto-clear ■ Hardware and software write protection ■ Power-up inadvertant write protection ■ 1,000,000 Program/erase cycles ■ 100 year data retention ■ Industrial temperature ranges ■ RoHS-compliant packages For Ordering Information details, see page 14. PIN CONFIGURATION FUNCTIONAL SYMBOL PDIP (L) SOIC (V, X) TSSOP (Y) TDFN (VP2) VCC SOIC (W) ORG CS 1 8 VCC NC 1 8 ORG SK 2 7 NC VCC 2 7 GND DI 3 6 ORG CS 3 6 DO DO 4 5 GND SK 4 5 DI CS CAT93C46 DO SK DI GND PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC +1.8 to 5.5V Power Supply GND Ground ORG Memory Organization NC No Connection Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1106, Rev. E CAT93C46 ABSOLUTE MAXIMUM RATINGS* Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground * (1) -0.5 V to +6.5 V Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS(2) Symbol NEND(*) TDR Parameter Endurance Data Retention Min 1,000,000 Units Program/ Erase Cycles 100 Years (*) Block Mode, VCC = 5.0V, 25°C D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, TA=-40°C to +85°C, unless otherwise specified. Symbol Parameter Test Conditions ICC1 Power Supply Current (Write) ICC2 Min Typ Max Units fSK = 1MHz VCC = 5.0V 3 mA Power Supply Current (Read) fSK = 1MHz VCC = 5.0V 500 µA ISB1 Power Supply Current (Standby) (x8 Mode) VIN=GND or VCC, CS =GND ORG=GND 10 µA ISB2 Power Supply Current (Standby) (x16Mode) VIN=GND or VCC, CS =GND ORG=Float or VCC 10 µA ILI Input Leakage Current VIN = GND to VCC 2 µA ILO Output Leakage Current VOUT = GND to VCC, CS = GND 2 µA VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 VCC + 1 V VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 VCC x 0.2 V VIH2 Input High Voltage 1.8V ≤ VCC < 4.5V VCC x 0.7 VCC+1 V VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V IOL = 2.1mA 0.4 V VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V IOH = -400µA VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V IOL = 1mA VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V IOH = -100µA 0 2.4 V 0.2 VCC - 0.2 V V Note: (1) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC +0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC +1.5V, for periods of less than 20 ns. (2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 2 Doc No. 1106, Rev. E CAT93C46 PIN CAPACITANCE TA=25°C, f=1MHz, VCC=5V Symbol COUT (1) CIN(1) Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Min Typ Max Units VOUT=0V 5 pF VIN=0V 5 pF A.C. CHARACTERISTICS VCC = +1.8V to +5.5V, TA=-40°C to +85°C, unless otherwise specified. Limits Symbol Parameter Min tCSS CS Setup Time 50 ns tCSH CS Hold Time 0 ns tDIS DI Setup Time 100 ns tDIH DI Hold Time 100 ns tPD1 Output Delay to 1 0.25 µs tPD0 Output Delay to 0 0.25 µs tHZ(1) Output Delay to High-Z 100 ns tEW Program/Erase Pulse Width 10 ms tCSMIN Minimum CS Low Time 0.25 µs tSKHI Minimum SK High Time 0.25 µs tSKLOW Minimum SK Low Time 0.25 µs tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency DC Max Units 0.25 µs 1000 kHz POWER-UP TIMING (1)(3) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms NOTES: (1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (2) Test conditions according to “AC Test Conditions” table. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc No. 1106, Rev. E CAT93C46 A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages Output Load ≤ 50ns 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V 0.2VCC to 0.7VCC 1.8V ≤ VCC ≤ 4.5V 0.5VCC 1.8V ≤ VCC ≤ 4.5V Current Source IOLmax/IOHmax; CL=100pF DEVICE OPERATION The CAT93C46 is a 1024-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C46 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 10-bit instructions control the reading, writing and erase operations of the device. The CAT93C46 operates on a single power supply and will generate on chip the high voltage required during any write operation. flag can be disabled only in Ready state; no change is allowed in Busy state. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organization). Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C46 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status during a write operation. The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The Ready/Busy Erase/Write Enable and Disable The CAT93C46 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C46 write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. INSTRUCTION SET Address Data Instruction Start Bit Opcode x8 x16 READ 1 10 A6-A0 A5-A0 Read Address AN– A0 ERASE 1 11 A6-A0 A5-A0 Clear Address AN– A0 WRITE 1 01 A6-A0 A5-A0 EWEN 1 00 11XXXXX 11XXXX Write Enable EWDS 1 00 00XXXXX 00XXXX Write Disable ERAL 1 00 10XXXXX 10XXXX Clear All Addresses WRAL 1 00 01XXXXX 01XXXX © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 4 x8 D7-D0 D7-D0 x16 D15-D0 D15-D0 Comments Write Address AN– A0 Write All Addresses Doc No. 1106, Rev. E CAT93C46 Figure 1. Sychronous Data Timing tSKLOW tSKHI tCSH SK tDIS tDIH VALID DI VALID tCSS CS tDIS tPD0,tPD1 DO tCSMIN DATA VALID Figure 2. Read Instruction Timing SK tCSMIN CS STANDBY AN DI 1 1 AN—1 A0 0 DO tHZ tPD0 HIGH-Z HIGH-Z 0 DN DN—1 D1 D0 Figure 3. EWEN/EWDS Instruction Timing SK STANDBY CS DI 1 0 0 * * ENABLE=11 DISABLE=00 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 1106, Rev. E CAT93C46 Write Erase All After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking for auto-clear and data store cycles on the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Erase Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Write All Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Figure 4. Write Instruction Timing SK tCSMIN AN DI STANDBY STATUS VERIFY CS 1 0 AN-1 A0 DN D0 1 tSV DO tHZ BUSY HIGH-Z READY HIGH-Z tEW © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 6 Doc No. 1106, Rev. E CAT93C46 Figure 5. Erase Instruction Timing SK STATUS VERIFY CS AN DI 1 1 tCS A0 AN-1 STANDBY 1 tSV tHZ HIGH-Z DO BUSY READY HIGH-Z tEW Figure 6. ERAL Instruction Timing SK CS STATUS VERIFY STANDBY tCS DI 1 0 0 1 0 tSV tHZ HIGH-Z DO BUSY READY HIGH-Z tEW Figure 7. WRAL Instruction Timing SK CS STATUS VERIFY STANDBY tCSMIN DI 1 0 0 0 DN 1 D0 tSV tHZ DO BUSY READY HIGH-Z tEW © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc No. 1106, Rev. E CAT93C46 8-LEAD 300 MIL WIDE PLASTIC DIP (L) E1 E D A2 A A1 L e eB b2 b SYMBOL A A1 A2 b b2 D E E1 e eB L MIN NOM MAX 4.57 0.38 3.05 0.36 1.14 9.02 7.62 6.09 7.87 0.115 0.46 7.87 6.35 2.54 BSC 0.130 3.81 0.56 1.77 10.16 8.25 7.11 9.65 0.150 24C16_8-LEAD_DIP_(300P).eps Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8 Doc No. 1106, Rev. E CAT93C46 8-LEAD 150 MIL WIDE SOIC (V, W) E1 E h x 45 D C A θ1 e A1 L b SYMBOL MIN A1 A b C D E E1 e h L θ1 0.10 1.35 0.33 0.19 4.80 5.80 3.80 NOM MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00 1.27 BSC 0.25 0.40 0° 0.50 1.27 8° 24C16_8-LEAD_SOIC.eps Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc No. 1106, Rev. E CAT93C46 8-LEAD 208 MIL SOIC (X) E b D c A θ1 e A1 L SYMBOL MIN A1 A b c D E E1 e L θ1 0.05 NOM MAX 0.25 2.03 0.48 0.25 5.33 8.26 5.38 0.36 0.19 5.13 7.75 5.13 1.27 BSC 0.51 0° 0.76 8° Notes: 1. All dimensions are in millimeters. 2. Complies with EIAJ specification EDR-7320. 3. D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs shall not exceed 0.06in per side. 4. E1 does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.010in per side. 5. Lead span/stand off height/coplanarity are considered as special characteristic (A1). © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 10 Doc No. 1106, Rev. E CAT93C46 8-LEAD TSSOP (Y) D 5 8 SEE DETAIL A c E E1 E/2 GAGE PLANE 4 1 PIN #1 IDENT. 0.25 θ1 L A2 SEATING PLANE SEE DETAIL A A e A1 b SYMBOL A A1 A2 b c D E E1 e L θ1 MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00 NOM 0.90 3.00 6.4 4.40 0.65 BSC 0.60 MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00 Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MO-153 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc No. 1106, Rev. E CAT93C46 8-PAD TDFN 2X3 PACKAGE (VP2) A E PIN 1 INDEX AREA A1 D D2 A2 A3 SYMBOL MIN NOM MAX A A1 A2 A3 b D D2 E E2 e L 0.70 0.00 0.45 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30 0.80 0.05 0.65 0.20 1.90 1.30 2.90 1.20 0.20 E2 0.30 2.10 1.50 3.10 1.40 0.40 PIN 1 ID L b e 3xe TDFN2X3 (03).eps Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-229. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 12 Doc No. 1106, Rev. E CAT93C46 PACKAGE MARKING 8-Lead PDIP 8-Lead SOIC 93C46LI FYYWWN CSI 93C46L I YY WW N F 93C46VI FYYWWN = Catalyst Semiconductor, Inc. = Device Code = Temperature Range = Production Year = Production Week = Product Revision = Lead Finish 4 = NiPdAu 3 = MatteTin CSI 93C46V I YY WW N F 8-Lead TSSOP = Catalyst Semiconductor, Inc. = Device Code = Temperature Range = Production Year = Production Week = Product Revision = Lead Finish 4 = NiPdAu 3 = MatteTin 8-Lead TDFN E K N NNN YM YMNF 93C46I Y = Production Year M = Production Month N = Product Revision 93C46 = Device Code I = Industrial Temperature Range F = Lead Finish 4 = NiPdAu 3 = MatteTin © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice EK EW N Y M = Device Code (NiPdAu)* = Device Code (Matte Tin)* = Traceability Code = Production Year = Production Month * The product revision is included in Device Code 13 Doc No. 1106, Rev. E CAT93C46 EXAMPLE OF ORDERING INFORMATION Prefix Device # CAT 93C46 Optional Company ID Suffix V Product Number 93C46 L V W X Y VP2 –G I Temperature Range I = Industrial (-40°C - 85°C) Package = PDIP = SOIC, JEDEC = SOIC, JEDEC = SOIC, EIAJ(4) = TSSOP = TDFN (2X3mm) T3 Tape & Reel T: Tape & Reel 2: 2000/Reel(4) 3: 3000/Reel Lead Finish Blank: Matte-Tin G: NiPdAu Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT93C46VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel). (4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C46XI-T2. (5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 14 Doc No. 1106, Rev. E REVISION HISTORY Date 12/01/05 Revision Comments A Initial Issue 12/08/05 B Update D.C Operating Characteristics 02/22/06 C Update Pin Configuration Update A.C. Charateristics Update Package Dimensions Update Ordering Information Update Package Marking 05/24/06 D Update Pin Configuration Update Pin Functions Update D.C. Operating Charateristics Update A.C. Charateristics Update Device Operation Update Package Marking Remove Tape and Reel Update Example of Package Information 08/03/06 E Update D.C. Operating Charateristics Update Test Condition for Pin Capacitance Update A.C. Test Conditions Update Device Operation Add 8 Lead 208 mil SOIC (X) Package Update Package Marking Update Example of Ordering Information Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: 1106 E 08/03/06