CAT93C66VI-G

CAT93C66 4 kb Microwire Serial CMOS EEPROM Description The CAT93C66 is a 4 kb CMOS Serial EEPROM device which is organized as either 256 registers of 16 bits (ORG pin at VCC) or 512 registers of 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The device features sequential read and self−timed internal write with auto−clear. On−chip Power−On Reset circuitry protects the internal logic against powering up in the wrong state. Features • • • • • • • • • • • • High Speed Operation: 2 MHz 1.8 V to 5.5 V Supply Voltage Range Selectable x8 or x16 Memory Organization: CAT93C66 Sequential Read Software Write Protection Power−up Inadvertent Write Protection Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial Temperature Ranges 8−lead SOIC Package This Device is Pb−Free, Halogen Free/BFR Free, and RoHS Compliant www.onsemi.com SOIC−8 V SUFFIX CASE 751BD PIN CONFIGURATION (Top View) 1 CS 8 VCC SK 2 7 NC DI 3 6 ORG DO 4 5 GND SOIC (V) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. VCC ORG CS SK CAT93C66 DO DI GND Figure 1. Functional Symbols CAT93C66 Selectable Organization: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected, then an internal pull−up device will select the x16 organization. © Semiconductor Components Industries, LLC, 2015 March, 2019 − Rev. 14 1 Publication Order Number: CAT93C66/D CAT93C66 Table 1. PIN FUNCTION Pin Name Function Pin Name Function CS Chip Select VCC Power Supply SK Clock Input GND Ground DI Serial Data Input ORG Memory Organization DO Serial Data Output NC No Connection Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature −65 to +150 °C Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 3. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter NEND (Note 3) TDR Endurance Data Retention Min Units 1,000,000 Program / Erase Cycles 100 Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Block Mode, VCC = 5 V, 25°C. Table 4. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = −40°C to +85°C unless otherwise specified.) Symbol Parameter Test Conditions Min Max Units ICC1 Power Supply Current (Write) fSK = 1 MHz, VCC = 5.0 V 1 mA ICC2 Power Supply Current (Read) fSK = 1 MHz, VCC = 5.0 V 500 mA ISB1 Power Supply Current (Standby) (x8 Mode) VIN = GND or VCC, CS = GND ORG = GND TA = −40°C to +85°C 2 mA ISB2 Power Supply Current (Standby) (x16 Mode) VIN = GND or VCC, CS = GND ORG = Float or VCC TA = −40°C to +85°C 1 mA ILI Input Leakage Current VIN = GND to VCC TA = −40°C to +85°C 1 mA ILO Output Leakage Current VOUT = GND to VCC, CS = GND TA = −40°C to +85°C 1 mA VIL1 Input Low Voltage 4.5 V ≤ VCC < 5.5 V −0.1 0.8 V VIH1 Input High Voltage 4.5 V ≤ VCC < 5.5 V 2 VCC + 1 V VIL2 Input Low Voltage 1.8 V ≤ VCC < 4.5 V 0 VCC x 0.2 V VIH2 Input High Voltage 1.8 V ≤ VCC < 4.5 V VCC x 0.7 VCC + 1 V VOL1 Output Low Voltage 4.5 V ≤ VCC < 5.5 V, IOL = 2.1 mA 0.4 V VOH1 Output High Voltage 4.5 V ≤ VCC < 5.5 V, IOH = −400 mA VOL2 Output Low Voltage 1.8 V ≤ VCC < 4.5 V, IOL = 1 mA VOH2 Output High Voltage 1.8 V ≤ VCC < 4.5 V, IOH = −100 mA 2.4 V 0.2 VCC − 0.2 V V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 2 CAT93C66 Table 5. PIN CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V) Test Conditions Output Capacitance (DO) Symbol COUT (Note 4) CIN (Note 4) Max Units VOUT = 0 V 5 pF VIN = 0 V 5 pF Input Capacitance (CS, SK, DI, ORG) Min Typ 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. Table 6. A.C. CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = −40°C to +85°C, unless otherwise specified.) (Note 5) Limits Symbol Min Parameter Max Units tCSS CS Setup Time 50 ns tCSH CS Hold Time 0 ns tDIS DI Setup Time 100 ns tDIH DI Hold Time 100 ns tPD1 Output Delay to 1 0.25 tPD0 Output Delay to 0 0.25 ms Output Delay to High−Z 100 ns 5 ms tHZ (Note 6) tEW Program/Erase Pulse Width ms tCSMIN Minimum CS Low Time 0.25 ms tSKHI Minimum SK High Time 0.25 ms tSKLOW Minimum SK Low Time 0.25 tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency ms DC 0.25 ms 2000 kHz 5. Test conditions according to “A.C. Test Conditions” table. 6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. Table 7. POWER−UP TIMING (Notes 7, 8) Parameter Symbol Max Units tPUR Power−up to Read Operation 1 ms tPUW Power−up to Write Operation 1 ms 7. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 8. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. www.onsemi.com 3 CAT93C66 Table 8. A.C. TEST CONDITIONS Input Rise and Fall Times ≤ 50 ns Input Pulse Voltages 0.4 V to 2.4 V 4.5 V ≤ VCC ≤ 5.5 V Timing Reference Voltages 0.8 V, 2.0 V 4.5 V ≤ VCC ≤ 5.5 V Input Pulse Voltages 0.2 VCC to 0.7 VCC 1.8 V ≤ VCC ≤ 4.5 V Timing Reference Voltages 0.5 VCC 1.8 V ≤ VCC ≤ 4.5 V Output Load Current Source IOLmax/IOHmax; CL = 100 pF Device Operation The CAT93C66 is a 4096−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C66 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 11−bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 12−bit instructions control the reading, writing and erase operations of the device. The device operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The serial communication protocol follows the timing shown in Figure 2. The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical “1” start bit, a 2−bit (or 4−bit) opcode, 8−bit address (an additional bit when organized X8) and for write operations a 16−bit data field (8−bit for X8 organizations). The instruction format is shown in Instruction Set table. Table 9. INSTRUCTION SET Address Data Instruction Start Bit Opcode x8 x16 READ 1 10 A8−A0 A7−A0 Read Address AN – A0 ERASE 1 11 A8−A0 A7−A0 Clear Address AN – A0 WRITE 1 01 A8−A0 A7−A0 EWEN 1 00 11XXXXXXX 11XXXXXX Write Enable EWDS 1 00 00XXXXXXX 00XXXXXX Write Disable ERAL 1 00 10XXXXXXX 10XXXXXX Clear All Addresses WRAL 1 00 01XXXXXXX 01XXXXXX www.onsemi.com 4 x8 D7−D0 D7−D0 x16 D15−D0 D15−D0 Comments Write Address AN – A0 Write All Addresses CAT93C66 Read word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. The READ instruction timing is illustrated in Figure 3. Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C66 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). For the CAT93C66 after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data tSKHI Erase/Write Enable and Disable The device powers up in the write disable state. Any writing after power−up or after an EWDS (erase/write disable) instruction must first be preceded by the EWEN (erase/write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C66 write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. The EWEN and EWDS instructions timing is shown in Figure 4. tSKLOW tCSH SK tDIS tDIH VALID DI VALID tCSS CS tPD0, tPD1 tDIS DO tCSMIN DATA VALID Figure 2. Synchronous Data Timing SK CS AN DI 1 1 AN−1 Don’t Care A0 0 tPD0 DO HIGH−Z Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Figure 3. READ Instruction Timing www.onsemi.com 5 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . CAT93C66 Write Erase After receiving a WRITE command (Figure 5), address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C66 can be determined by selecting the device and polling the DO pin. Since this device features Auto−Clear before write, it is NOT necessary to erase a memory location before it is written into. Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN (Figure 6). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C66 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. SK STANDBY CS DI 1 0 0 * ENABLE = 11 DISABLE = 00 * Figure 4. EWEN/EWDS Instruction Timing SK tCSMIN CS AN AN−1 DI 1 0 A0 DN STATUS VERIFY D0 STANDBY 1 tSV HIGH−Z DO BUSY READY tHZ HIGH−Z tEW Figure 5. Write Instruction Timing SK CS AN DI DO 1 1 AN−1 A0 tCS STATUS VERIFY STANDBY 1 tSV HIGH−Z BUSY tEW Figure 6. Erase Instruction Timing www.onsemi.com 6 tHZ READY HIGH−Z CAT93C66 Erase All Write All Upon receiving an ERAL command (Figure 7), the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the device can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN (Figure 8). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the device can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. SK CS STATUS VERIFY STANDBY tCS DI 1 0 1 0 0 tSV tHZ HIGH−Z DO BUSY READY HIGH−Z tEW Figure 7. ERAL Instruction Timing SK CS STATUS VERIFY STANDBY tCSMIN DI 1 0 0 0 1 DN D0 tSV tHZ DO BUSY READY HIGH−Z tEW Figure 8. WRAL Instruction Timing Table 10. ORDERING INFORMATION OPN CAT93C66VI−GT3 Specific Device Marking Pkg Type Temperature Range Lead Finish Shipping 93C66D SOIC−8, JEDEC I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3000 Units / Reel 9. All packages are RoHS−compliant (Lead−free, Halogen−free). 10. The standard lead finish is NiPdAu. 11. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 12. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 13. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com www.onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 DATE 19 DEC 2008 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 A θ c e b SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. 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