CAT93C76LET2

CAT93C76 8-Kb Microwire Serial EEPROM Description The CAT93C76 is an 8−Kb Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC or Not Connected) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C76 is manufactured using ON Semiconductor’s advanced CMOS EEPROM floating gate technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8−pin PDIP, SOIC, TSSOP and 8−pad TDFN packages. Features http://onsemi.com SOIC−8 V SUFFIX CASE 751BD TDFN−8 ZD4 SUFFIX CASE 511AL • • • • • • • • • • • • • High Speed Operation: 3 MHz @ VCC ≥ 2.5 V Low Power CMOS Technology 1.8 to 5.5 Volt Operation Selectable x8 or x16 Memory Organization Self−timed Write Cycle with Auto−clear Software Write Protection Power−up Inadvertant Write Protection 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Ranges Sequential Read “Green” Package Option Available This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant VCC ORG CS SK GND DI DO PDIP−8 L SUFFIX CASE 646AA TSSOP−8 Y SUFFIX CASE 948AL PIN CONFIGURATION CS SK DI DO 1 VCC NC ORG GND PDIP (L), SOIC (V), TSSOP (Y), TDFN (ZD4) PIN FUNCTION Pin Name CS SK DI DO VCC GND ORG NC Function Chip Select Serial Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization No Connection Figure 1. Functional Symbol NOTE: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected, then an internal pull−up device will select the x16 organization. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. © Semiconductor Components Industries, LLC, 2009 August, 2009 − Rev. 3 1 Publication Order Number: CAT93C76/D CAT93C76 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) VCC with Respect to Ground Lead Soldering Temperature (10 seconds) Output Short Circuit Current (Note 2) Ratings −55 to +125 −65 to +150 −2.0 to +VCC +2.0 −2.0 to +7.0 300 100 Units °C °C V V °C mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns. 2. Output shorted for no more than one second. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol NEND (Note 3) TDR (Note 3) VZAP (Note 3) ILTH (Notes 3, 4) Parameter Endurance Data Retention ESD Susceptibility Latch−Up Reference Test Method MIL−STD−883, Test Method 1033 MIL−STD−883, Test Method 1008 MIL−STD−883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2,000 100 Units Cycles / Byte Years V mA 3. These parameters are tested initially and after a design or process change that affects the parameter. 4. Latch−up protection is provided for stresses up to 100 mA on I/O pins from −1 V to VCC + 1 V. Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V unless otherwise specified.) Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO ILORG VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16 Mode) Input Leakage Current Output Leakage Current ORG Pin Leakage Current Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Conditions fSK = 1 MHz, VCC = 5.0 V fSK = 1 MHz, VCC = 5.0 V CS = 0 V, ORG = GND CS = 0 V, ORG = Float or VCC VIN = 0 V to VCC VOUT = 0 V to VCC, CS = 0 V ORG = GND or ORG = VCC 4.5 V v VCC v 5.5 V 4.5 V v VCC v 5.5 V 1.8 V v VCC < 4.5 V 1.8 V v VCC < 4.5 V 4.5 V v VCC v 5.5 V, IOL = 2.1 mA 4.5 V v VCC v 5.5 V, IOH = −400 mA 1.8 V v VCC < 4.5 V, IOL = 100 mA 1.8 V v VCC < 4.5 V, IOH = −100 mA VCC − 0.2 2.4 0.1 −0.1 2 0 VCC x 0.7 Min Typ 1 300 2 0 (Note 5) 0 (Note 5) 0 (Note 5) 1 Max 3 500 10 10 10 10 10 0.8 VCC + 1 VCC x 0.2 VCC + 1 0.4 Units mA mA mA mA mA mA mA V V V V V V V V 5. 0 mA is defined as less than 900 nA. Table 4. PIN CAPACITANCE (Note 3) Symbol COUT CIN Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Conditions VOUT = 0 V VIN = 0 V Min Typ Max 5 5 Units pF pF http://onsemi.com 2 CAT93C76 Table 5. INSTRUCTION SET (Note 6) Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Start Bit 1 1 1 1 1 1 1 Address Opcode 10 11 01 00 00 00 00 x8 A10−A0 A10−A0 A10−A0 11XXXXXXXXX 00XXXXXXXXX 10XXXXXXXXX 01XXXXXXXXX x16 A9−A0 A9−A0 A9−A0 11XXXXXXXX 00XXXXXXXX 10XXXXXXXX 01XXXXXXXX D7−D0 D15−D0 D7−D0 D15−D0 x8 Data x16 Comments Read Address AN– A0 Clear Address AN– A0 Write Address AN– A0 Write Enable Write Disable Clear All Addresses Write All Addresses 6. Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or “0” for READ, WRITE and ERASE commands. Table 6. A.C. CHARACTERISTICS Limits VCC = 1.8 V − 2.5 V Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ (Note 8) tEW tCSMIN tSKHI tSKLOW tSV SKMAX Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High−Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 200 250 250 250 1000 DC CL = 100 pF (Note 7) Test Conditions Min 100 0 100 100 250 250 150 5 150 150 150 100 3000 Max VCC = 2.5 V − 5.5 V Min 50 0 50 50 150 150 100 5 Max Units ns ns ns ns ns ns ns ms ns ns ns ns kHz 7. The input levels and timing reference points are shown in the “AC Test Conditions” table. 8. These parameters are tested initially and after a design or process change that affects the parameter. Table 7. POWER−UP TIMING (Notes 8, 9) Symbol tPUR tPUW Power−up to Read Operation Power−up to Write Operation Parameter Max 1 1 Units ms ms 9. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Table 8. A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages ≤ 50 ns 0.4 V to 2.4 V 0.8 V, 2.0 V 0.2 VCC to 0.7 VCC 0.5 VCC 4.5 V v VCC v 5.5 V 4.5 V v VCC v 5.5 V 1.8 V v VCC v 4.5 V 1.8 V v VCC v 4.5 V http://onsemi.com 3 CAT93C76 Device Operation The CAT93C76 is a 8192−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C76 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 13−bit instructions control the read, write and erase operations of the device. When organized as X8, seven 14−bit instructions control the read, write and erase operations of the device. The CAT93C76 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address (an additional bit when organized X8) and for write operations a 16−bit data field (8−bit for X8 organizations). The most significant bit of the address is “don’t care” but it must be present. tSKHI SK tDIS DI tCSS CS tDIS DO tPD0, tPD1 DATA VALID tCSMN VALID VALID tDIH Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C76 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). For the CAT93C76, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. Since this device features Auto−Clear before write, it is NOT necessary to erase a memory location before it is written into. tSKLOW tCSH Figure 2. Synchronous Data Timing http://onsemi.com 4 CAT93C76 SK CS AN DI 1 1 0 AN−1 A0 Don’t Care DO HIGH−Z Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . Figure 3. READ Instruction Timing SK tCSMIN CS AN DI 1 0 1 tSV DO HIGH−Z tEW BUSY READY tHZ HIGH−Z AN−1 A0 DN D0 STATUS VERIFY STANDBY Figure 4. WRITE Instruction Timing http://onsemi.com 5 CAT93C76 Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Erase/Write Enable and Disable determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Write All The CAT93C76 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C76 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Erase All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Note 1: After the last data bit has been sampled, Chip Select (CS) must be brought Low before the next rising edge of the clock (SK) in order to start the self-timed high voltage cycle. This is important because if CS is brought low before or after this specific frame window, the addressed location will not be programmed or erased. Power-On Reset (POR) Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be The CAT93C76 incorporates Power-On Reset (POR) circuitry which protects the device against malfunctioning while VCC is lower than the recommended operating voltage. The device will power up into a read-only state and will power-down into a reset state when VCC crosses the POR level of ~1.3 V. SK CS AN DI 1 1 1 tSV DO HIGH−Z AN−1 A0 STATUS VERIFY tCS STANDBY tHZ BUSY tEW READY HIGH−Z Figure 5. ERASE Instruction Timing http://onsemi.com 6 CAT93C76 SK CS STANDBY DI 1 0 0 * * ENABLE = 11 DISABLE = 00 Figure 6. EWEN/EWDS Instruction Timing SK CS STATUS VERIFY tCS STANDBY DI 1 0 0 1 0 tSV tHZ BUSY tEW READY HIGH−Z DO HIGH−Z Figure 7. ERAL Instruction Timing SK CS STATUS VERIFY tCSMIN STANDBY DI 1 0 0 0 1 DN D0 tSV tHZ BUSY tEW READY HIGH−Z DO Figure 8. WRAL Instruction Timing http://onsemi.com 7 CAT93C76 PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL A A1 A2 b E1 b2 c D E E1 e eB PIN # 1 IDENTIFICATION D L 7.87 2.92 3.30 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 BSC 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25 7.11 MIN NOM MAX 5.33 TOP VIEW E A A2 A1 b2 L c e SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. b eB END VIEW http://onsemi.com 8 CAT93C76 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL A A1 b c E1 E D E E1 e h L PIN # 1 IDENTIFICATION TOP VIEW 0.25 0.40 MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.50 1.27 NOM MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00 θ 0º 8º D h A1 A θ c e SIDE VIEW b L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 9 CAT93C76 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL A A1 A2 b E1 E c D E E1 e L L1 MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 NOM MAX 1.20 0.15 0.90 1.05 0.30 0.20 3.00 6.40 4.40 0.65 BSC 1.00 REF 3.10 6.50 4.50 0.50 0.60 0.75 θ e 0º 8º TOP VIEW D A2 A q1 c A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. L1 END VIEW L http://onsemi.com 10 CAT93C76 PACKAGE DIMENSIONS TDFN8, 3x3 CASE 511AL−01 ISSUE A D A e b L E E2 PIN#1 ID PIN#1 INDEX AREA A1 D2 TOP VIEW SIDE VIEW BOTTOM VIEW SYMBOL A A1 A3 b D D2 E E2 e L MIN 0.70 0.00 0.23 2.90 2.20 2.90 1.40 0.20 NOM 0.75 0.02 0.20 REF 0.30 3.00 −−− 3.00 −−− 0.65 TYP 0.30 MAX 0.80 0.05 0.37 3.10 2.50 3.10 1.80 0.40 A1 FRONT VIEW A A3 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229. http://onsemi.com 11 CAT93C76 Example of Ordering Information Prefix CAT Device # 93C76 Suffix V I −G T3 Company ID Product Number 93C76 Temperature Range I = Industrial (−40°C to +85°C) E = Extended (−40°C to +125°C) Lead Finish G: NiPdAu Blank: Matte−Tin Tape & Reel (Note 14) T: Tape & Reel 2: 2,000 Units / Reel (Note 15) 3: 3,000 Units / Reel Package L: PDIP V: SOIC, JEDEC Y: TSSOP ZD4: TDFN (3 x 3 mm) 10. All packages are RoHS−compliant (Lead−free, Halogen−free). 11. The standard lead finish is NiPdAu. 12. The device used in the above example is a CAT93C76VI−GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000 / Reel). 13. Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA). For additional information, please contact your ON Semiconductor sales office. 14. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 15. For TDFN 3 x 3 mm package Tape and Reel = 2,000 / Reel, all others = 3,000 / Reel. 16. For additional package and temperature options, please contact your nearest ON Semiconductor sales office. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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