DATA SHEET
www.onsemi.com
EEPROM Serial 16-Kb
Microwire
CAT93C86B
SOIC−8
V SUFFIX
CASE 751BD
SOIC−8
X SUFFIX
CASE 751BE
UDFN−8
HU4 SUFFIX
CASE 517AZ
TSSOP−8
Y SUFFIX
CASE 948AL
Description
The CAT93C86B is a 16−Kb Serial EEPROM memory device
which is configured as either registers of 16 bits (ORG pin at VCC) or 8
bits (ORG pin at GND). Each register can be written (or read) serially
by using the DI (or DO) pin. The CAT93C86B features a self−timed
internal write with auto−clear. On−chip Power−On Reset circuit
protects the internal logic against powering up in the wrong state.
PIN CONFIGURATION
Features
High Speed Operation: 4 MHz (5 V), 2 MHz (1.8 V)
1.8 V (1.65 V*) to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Self−timed Write Cycle with Auto−clear
Sequential Read
Hardware and Software Write Protection
Power−up Inadvertent Write Protection
Low Power CMOS Technology
Program Enable (PE) Pin
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Ranges
8−pin SOIC, TSSOP and 8−pad UDFN Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant†
VCC
CS
SK
DI
DO
DI
CS
CAT93C86B
SK
VCC
PE
ORG
GND
SOIC (V, X),
TSSOP (Y),
UDFN (HU4)
PIN FUNCTION
Pin Name
Function
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
VCC
Power Supply
GND
Ground
ORG
Memory Organization
PE
ORG
1
Program Enable
Note: When the ORG pin is connected to VCC, the
x16 organization is selected. When it is connected
to ground, the x8 pin is selected. If the ORG pin is
left unconnected, then an internal pull−up device will
select the x16 organization.
DO
PE
ORDERING INFORMATION
GND
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Figure 1. Functional Symbol
*CAT93C86Bxx−xxL (TA = −205C to +855C)
†For additional information on our Pb−Free strategy and soldering details, please
download the onsemi Soldering and Mounting Techniques Reference Manual,
SOLDERRM/D.
Semiconductor Components Industries, LLC, 2013
April, 2023 − Rev. 4
1
Publication Order Number:
CAT93C86B/D
CAT93C86B
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
−65 to +150
C
Voltage on Any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Parameter
Symbol
NEND (Note 3)
TDR
Endurance
Min
Units
1,000,000
Program / Erase Cycles
100
Years
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, VCC = 5 V, 25C.
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = +1.8 V to +5.5 V, TA = −40C to +125C, VCC = +1.65 V to +5.5 V, TA = −20C to +85C unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
ICC1
Supply Current (Write)
Write, VCC = 5.0 V
ICC2
Supply Current (Read)
Read, DO open, fSK = 2 MHz, VCC = 5.0 V
ISB1
Standby Current
(x8 Mode)
VIN = GND or VCC
CS = GND, ORG = GND
Standby Current
(x16 Mode)
ISB2
ILI
Input Leakage Current
Max
Units
2
mA
500
mA
TA = −40C to +85C
2
mA
TA = −40C to +125C
5
VIN = GND or VCC
CS = GND,
ORG = Float or VCC
TA = −40C to +85C
1
TA = −40C to +125C
3
VIN = GND to VCC
TA = −40C to +85C
1
TA = −40C to +125C
2
TA = −40C to +85C
1
mA
mA
ILO
Output Leakage
Current
VOUT = GND to VCC
CS = GND
VIL1
Input Low Voltage
4.5 V VCC < 5.5 V
−0.1
0.8
V
VIH1
Input High Voltage
4.5 V VCC < 5.5 V
2
VCC + 1
V
VIL2
Input Low Voltage
1.65 V VCC < 4.5 V
0
VCC x 0.2
V
VIH2
Input High Voltage
1.65 V VCC < 4.5 V
VCC x 0.7
VCC + 1
V
VOL1
Output Low Voltage
4.5 V VCC < 5.5 V, IOL = 3 mA
0.4
V
VOH1
Output High Voltage
4.5 V VCC < 5.5 V, IOH = −400 mA
VOL2
Output Low Voltage
1.65 V VCC < 4.5 V, IOL = 1 mA
VOH2
Output High Voltage
1.65 V VCC < 4.5 V, IOH = −100 mA
TA = −40C to +125C
mA
2
2.4
V
0.2
VCC − 0.2
V
V
Table 4. PIN CAPACITANCE (Note 4)
Symbol
COUT
CIN
Test
Conditions
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Min
Typ
Max
Units
VOUT = 0 V
5
pF
VIN = 0 V
5
pF
Table 5. POWER−UP TIMING (Notes 4, 5)
Symbol
Max
Units
tPUR
Power−up to Read Operation
Parameter
1
ms
tPUW
Power−up to Write Operation
1
ms
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2
CAT93C86B
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall Times
50 ns
Input Pulse Voltages
0.4 V to 2.4 V
4.5 V VCC 5.5 V
Timing Reference Voltages
0.8 V, 2.0 V
4.5 V VCC 5.5 V
Input Pulse Voltages
0.2 VCC to 0.7 VCC
1.65 V VCC 4.5 V
Timing Reference Voltages
0.5 VCC
1.65 V VCC 4.5 V
Output Load
Current Source IOLmax/IOHmax; CL = 100 pF
4. These parameters are tested initially and after a design or process change that affects the parameter.
5. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 7. A.C. CHARACTERISTICS
(VCC = +1.8 V to +5.5 V, TA = −40C to +125C, VCC = +1.65 V to +5.5 V, TA = −20C to +85C unless otherwise specified.)
VCC < 4.5 V
Symbol
Min
Parameter
VCC > 4.5 V
Max
Min
Units
tCSS
CS Setup Time
tCSH
CS Hold Time
tDIS
DI Setup Time
tDIH
DI Hold Time
100
tPD1
Output Delay to 1
0.25
0.1
ms
tPD0
Output Delay to 0
0.25
0.1
ms
Output Delay to High−Z
100
100
ns
5
ms
tHZ (Note 6)
tEW
50
Max
50
ns
0
0
ns
100
50
ns
50
ns
Program/Erase Pulse Width
5
tCSMIN
Minimum CS Low Time
0.25
0.1
ms
tSKHI
Minimum SK High Time
0.25
0.1
ms
tSKLOW
Minimum SK Low Time
0.25
0.1
ms
tSV
Output Delay to Status Valid
SKMAX
Maximum Clock Frequency
0.25
DC
2000
DC
0.1
ms
4000
kHz
6. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. INSTRUCTION SET
Address
Data
Instruction
Start
Bit
Opcode
x8
x16
x8
x16
Comments
READ
1
10
A10−A0
A9−A0
Read Address AN– A0
ERASE
1
11
A10−A0
A9−A0
Clear Address AN– A0
WRITE
1
01
A10−A0
A9−A0
EWEN
1
00
11XXXXXXXXX
11XXXXXXXX
Write Enable
EWDS
1
00
00XXXXXXXXX
00XXXXXXXX
Write Disable
ERAL*
1
00
10XXXXXXXXX
10XXXXXXXX
Clear All Addresses
WRAL*
1
00
01XXXXXXXXX
01XXXXXXXX
*Not available at VCC < 1.8 V
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3
D7−D0
D7−D0
D15−D0
D15−D0
Write Address AN– A0
Write All Addresses
CAT93C86B
DEVICE OPERATION
The CAT93C86B is a 16,384−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C86B can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 13−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
14−bit instructions control the reading, writing and erase
operations of the device. The CAT93C86B operates on a
single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
Note: The Write, Erase, Write all and Erase all instructions
require PE = 1. If PE is left floating, 93C86B is in Program
Enabled mode. For Write Enable and Write Disable
instruction PE = don’t care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C86B will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle, the
device will automatically increment to the next address and
shift out the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues to
toggle, the device will keep incrementing to the next address
automatically until it reaches to the end of the address space,
then loops back to address 0. In the sequential READ mode,
only the initial data word is preceeded by a dummy zero bit.
All subsequent data words will follow without a dummy
zero bit.
Write
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of tCSMIN. The falling edge of CS will start the self clocking
clear and data store cycle of the memory location specified
in the instruction. The clocking of the SK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C86B can be
determined by selecting the device and polling the DO pin.
Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
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4
CAT93C86B
tSKHI
tSKLOW
tCSH
SK
tDIS
tDIH
VALID
DI
VALID
tCSS
CS
tPD0, tPD1
tDIS
DO
tCSMIN
DATA VALID
Figure 2. Synchronous Data Timing
SK
1
1
1
1
1
AN
AN−1
1
1
1
1
1
1
1
1
1
1
CS
DI
1
1
Don’t Care
A0
0
HIGH−Z
DO
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Figure 3. Read Instruction Timing
SK
tCSMIN
CS
AN AN−1
DI
DO
1
0
A0
DN
STATUS
VERIFY
D0
STANDBY
1
tSV
HIGH−Z
BUSY
READY
tEW
Figure 4. Write Instruction Timing
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5
tHZ
HIGH−Z
CAT93C86B
Erase
Erase All
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C86B can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The falling
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C86B can be
determined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to a
logical “1” state.
Erase/Write Enable and Disable
Write All
The CAT93C86B powers up in the write disable state.
Any writing after power−up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device is
removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C86B write and
clear instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from the
device regardless of the write enable/disable status.
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C86B can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
CS
AN
DI
DO
1
1
AN−1
A0
tCS
STATUS
VERIFY
STANDBY
1
tSV
HIGH−Z
BUSY
tEW
Figure 5. Erase Instruction Timing
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6
tHZ
READY
HIGH−Z
CAT93C86B
ORDERING INFORMATION
Order Number
Specific Device Marking
Package Type
Temperature Range
Shipping
CAT93C86BVI−GT3
93C86D
SOIC−8, JEDEC
I = Industrial
(−40C to +85C)
Tape & Reel,
3,000 Units / Reel
CAT93C86BVE−GT3
93C86D
SOIC−8, JEDEC
E = Extended
(−40C to +125C)
Tape & Reel,
3,000 Units / Reel
CAT93C86BYI−GT3
M86D
TSSOP−8
I = Industrial
(−40C to +85C)
Tape & Reel,
3,000 Units / Reel
CAT93C86BYE−GT3
M86D
TSSOP−8
E = Extended
(−40C to +125C)
Tape & Reel,
3,000 Units / Reel
CAT93C86BHU4I−GT3
M4U
UDFN−8
I = Industrial
(−40C to +85C)
Tape & Reel,
3,000 Units / Reel
CAT93C86BXI−T2
93C86D
SOIC−8, EIAJ
I = Industrial
(−40C to +85C)
Tape & Reel,
2,000 Units / Reel
CAT93C86BXE−T2
93C86D
SOIC−8, EIAJ
E = Extended
(−40C to +125C)
Tape & Reel,
2,000 Units / Reel
7. All packages are RoHS−compliant (Lead−free, Halogen−free).
8. The standard lead finish is NiPdAu.
9. For additional package and temperature options, please contact your nearest onsemi Sales office.
10. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
11. For detailed information and a breakdown of device nomenclature and numbering systems, please see the onsemi Device Nomenclature
document, TND310/D, available at www.onsemi.com
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE A
1
SCALE 2:1
PIN ONE
REFERENCE
0.10 C
B
A
D
L1
ÇÇ
ÇÇ
ÇÇ
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
EXPOSED Cu
DETAIL B
A
0.10 C
0.08 C
1
D2
ÉÉ
ÉÉ
ÇÇ
C
MOLD CMPD
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
A1
ALTERNATE
CONSTRUCTIONS
1
L
4
5
8X
e
XXXXX
A
WL
Y
W
G
BOTTOM VIEW
b
0.10
M
C A B
0.05
M
C
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.20
0.30
2.00 BSC
1.35
1.45
3.00 BSC
1.25
1.35
0.50 BSC
0.25
0.35
−−−
0.15
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
E2
8
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
DETAIL B
A3
A1
SIDE VIEW
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
0.10 C TOP VIEW
NOTE 4
DATE 23 MAR 2015
XXXXX
AWLYWG
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
1.56
8X
0.68
1.45 3.40
1
8X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON42552E
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
UDFN8, 2X3 EXTENDED PAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8, 150 mils
CASE 751BD
ISSUE O
E1
DATE 19 DEC 2008
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
MAX
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
A
θ
c
e
b
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34272E
SOIC 8, 150 MILS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP8, 4.4x3.0, 0.65P
CASE 948AL
ISSUE A
DATE 20 MAY 2022
q
q
GENERIC
MARKING DIAGRAM*
XXX
YWW
AG
XXX
Y
WW
A
G
= Specific Device Code
= Year
= Work Week
= Assembly Location
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34428E
TSSOP8, 4.4X3.0, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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