CD4724BCN

Revised May 2002 CD4724BC 8-Bit Addressable Latch General Description Features The CD4724BC is an 8-bit addressable latch with three address inputs (A0–A2), an active low enable input (E), active high clear input (CL), a data input (D) and eight outputs (Q0–Q7). ■ Wide supply voltage range: Data is entered into a particular bit in the latch when that is addressed by the address inputs and the enable (E) is LOW. Data entry is inhibited when enable (E) is HIGH. When clear (CL) and enable (E) are HIGH, all outputs are LOW. When clear (CL) is HIGH and enable (E) is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW). 3.0V to 15V ■ High noise immunity: 0.45 VDD (typ.) ■ Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS ■ Serial to parallel capability ■ Storage register capability ■ Random (addressable) data entry ■ Active high demultiplexing capability ■ Common active high clear Ordering Code: Order Number Package Number Package Description CD4724BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4724BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Mode Selection E CL L L Follows Data H L Hold Previous Holds Previous Data Data L H Follows Data Reset to “0” Demultiplexer H H Reset to “0” Reset to “0” Clear Addressed Latch Unaddressed Mode Latch Holds Previous Data Addressable Latch Memory Top View © 2002 Fairchild Semiconductor Corporation DS006003 www.fairchildsemi.com CD4724BC 8-Bit Addressable Latch October 1987 CD4724BC Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) (Note 2) −0.5V to +18 VDC DC Supply Voltage (VDD) Input Voltage (VIN) DC Supply Voltage (VDD) −0.5V to VDD +0.5 VDC −65°C to +150°C Storage Temperature (TS) 700 mW Small Outline 500 mW Symbol IDD VOL VOH VIL VIH IOL IOH IIN Note 2: VSS = 0V unless otherwise specified. 260°C DC Electrical Characteristics Parameter −55°C to +125°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and Electrical Characteristics” provide conditions for actual device operation. Lead Temperature (TL) (Soldering, 10 seconds) 0V to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3.0V to 15 VDC Input Voltage (VIN) (Note 2) −55°C Conditions Min +25°C Max Min Typ +125°C Max Min Max Quiescent Device VDD = 5V 5 0.02 5 150 Current VDD = 10V 10 0.02 10 300 VDD = 15V 20 0.02 20 600 LOW Level |IO| ≤ 1 µA Output Voltage VDD = 5V 0.05 0 0.05 0.05 VDD = 10V 0.05 0 0.05 0.05 VDD = 15V 0.05 0 0.05 0.05 HIGH Level |IO| ≤ 1 µA Output Voltage VDD = 5V 4.95 4.95 5.0 VDD = 10V 9.95 9.95 10 9.95 VDD = 15V 14.95 14.95 15 14.95 Units µA V 4.95 V LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 Input Voltage VDD = 10V, VO = 1V or 9V 3.0 4.5 3.0 3.0 VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 Input Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 5.5 7.0 VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 Current VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9 (Note 3) VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4 HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 Current VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9 (Note 3) VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4 Input Current VDD = 15V, VIN = 0V −0.1 −10−5 −0.1 −1.0 VDD = 15V, VIN = 15V 0.1 10−5 0.1 1.0 V V mA mA µA Note 3: IOL and IOH are tested one output at a time. 3 www.fairchildsemi.com CD4724BC Absolute Maximum Ratings(Note 1) CD4724BC AC Electrical Characteristics (Note 4) TA = 25°C, CL = 50 pF, RL = 200k, Input tr = tf = 20 ns, unless otherwise noted Symbol tPHL, tPLH tPLH, tPHL tPHL tPLH, tPHL tTHL, tTLH TWH, TWL tWH, tWL tWH tSU tH tSU tH CPD CIN Typ Max Propagation Delay Parameter VDD = 5V Conditions Min 200 400 Data to Output VDD = 10V 75 150 VDD = 15V 50 100 Propagation Delay VDD = 5V 200 400 Enable to Output VDD = 10V 80 160 VDD = 15V 60 120 Propagation Delay VDD = 5V 175 350 Clear to Output VDD = 10V 80 160 VDD = 15V 65 130 Propagation Delay VDD = 5V 225 450 Address to Output VDD = 10V 100 200 VDD = 15V 75 150 Transition Time VDD = 5V 100 200 (Any Output) VDD = 10V 50 100 VDD = 15V 40 80 Minimum Data VDD = 5V 100 200 Pulse Width VDD = 10V 50 100 VDD = 15V 40 80 Minimum Address VDD = 5V 200 400 Pulse Width VDD = 10V 100 200 VDD = 15V 65 125 Minimum Clear VDD = 5V 75 150 Pulse Width VDD = 10V 40 75 VDD = 15V 25 50 Minimum Setup Time VDD = 5V 40 80 Data to E VDD = 10V 20 40 VDD = 15V 15 30 Minimum Hold Time VDD = 5V 60 120 Data to E VDD = 10V 30 60 VDD = 15V 25 50 Minimum Setup Time VDD = 5V −15 50 Address to E VDD = 10V 0 30 VDD = 15V 0 20 Minimum Hold Time VDD = 5V −50 15 Address to E VDD = 10V −20 10 VDD = 15V −15 5 Power Dissipation Per Package 100 Capacitance (Note 5) Input Capacitance Any Input 5.0 Units ns ns ns ns ns ns ns ns ns ns ns ns pF 7.5 pF Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Dynamic power dissipation (PD) is given by: PD = (CPD + C L) VCC2f + PQ; where CL = load capacitance; f = frequency of operation; for further details, see Application Note AN-90, “Family Characteristics”. www.fairchildsemi.com 4 CD4724BC Switching Time Waveforms 5 www.fairchildsemi.com CD4724BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A www.fairchildsemi.com 6 CD4724BC 8-Bit Addressable Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com