CM1213A 1, 2 and 4-Channel Low Capacitance ESD Protection Arrays
Product Description
The CM1213A family of diode arrays has been designed to provide ESD protection for electronic components or subsystems requiring minimal capacitive loading. These devices are ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading. Each ESD channel consists of a pair of diodes in series which steer the positive or negative ESD current pulse to either the positive (VP) or negative (VN) supply rail. A Zener diode is embedded between VP and VN, offering two advantages. First, it protects the VCC rail against ESD strikes, and second, it eliminates the need for a bypass capacitor that would otherwise be needed for absorbing positive ESD strikes to ground. The CM1213A will protect against ESD pulses up to 8 kV per the IEC 61000−4−2 standard. These devices are particularly well−suited for protecting systems using high−speed ports such as USB 2.0, IEEE1394 (Firewire®, iLinkt), Serial ATA, DVI, HDMI and corresponding ports in removable storage, digital camcorders, DVD−RW drives and other applications where extremely low loading capacitance with ESD protection are required in a small package footprint.
Features
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SOT23−3 SO SUFFIX CASE 527AG
SOT143 SR SUFFIX CASE 527AF
SOT23−5 SO SUFFIX CASE 527AH
SOT23−6 SO SUFFIX CASE 527AJ
SC70−6 S7 SUFFIX CASE 419AD
MSOP−10 MR SUFFIX CASE 846AE
MARKING DIAGRAM
• One, Two, and Four Channels of ESD Protection • • • • • • •
XXXMG G 1 1
XXXMG G
Note: For 6 and 8−channel Devices, See the CM1213 Datasheet Provides ESD Protection to IEC61000−4−2 Level 4 • ±8 kV Contact Discharge Low Channel Input Capacitance of 0.85 pF Typical Minimal Capacitance Change with Temperature and Voltage Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for Differential Dignals Zener Diode Protects Supply Rail and Eliminates the Need for External By−pass Capacitors Each I/O Pin Can Withstand Over 1000 ESD Strikes* These Devices are Pb−Free and are RoHS Compliant
XXX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
Device CM1213A−01SO CM1213A−02SR CM1213A−02SO CM1213A−04SO CM1213A−04S7 CM1213A−04MR Package SOT23−3 (Pb−Free) Shipping† 3000/Tape & Reel
SOT143−4 3000/Tape & Reel (Pb−Free) SOT23−5 (Pb−Free) SOT23−6 (Pb−Free) SC70−6 (Pb−Free) MSOP−10 (Pb−Free) 3000/Tape & Reel 3000/Tape & Reel 3000/Tape & Reel 4000/Tape & Reel
Applications
• USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks and Peripherals • IEEE1394 Firewire® Ports at 400 Mbps / 800 Mbps • DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs, • • •
LCD Displays Serial ATA Ports in Desktop PCs and Hard Disk Drives PCI Express Ports General Purpose High−Speed Data Line ESD Protection
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
*Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes.
© Semiconductor Components Industries, LLC, 2011
July, 2011 − Rev. 7
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Publication Order Number: CM1213A/D
CM1213A
BLOCK DIAGRAM
VP CH1 CH1 VP CH2 CH4 VP CH3
VN CM1213A−01SO
VN CM1213A−02SR CM1213A−02SO
CH1 VN CH2 CM1213A−04SO CM1213A−04MR CM1213A−04S7
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CM1213A
Table 1. PIN DESCRIPTIONS
1−Channel, 3−Lead SOT23−3 Package (CM1213A−01SO) Pin 1 2 3 Name CH1 VP VN Type I/O PWR GND Description ESD Channel Positive voltage supply rail Negative voltage supply rail VP (2) 2 CH1 (1) Top View 1 D231 3 VN (3)
PACKAGE / PINOUT DIAGRAMS
3−Lead SOT23−3 2−Channel, 4−Lead SOT143−4 Package (CM1213A−02SR) Pin 1 2 3 4 Name VN CH1 CH2 VP Type GND I/O I/O PWR Description Negative voltage supply rail ESD Channel ESD Channel Positive voltage supply rail CH1 (2) 2 VN (1) Top View 1 D232 3 CH2 (3) 4−Lead SOT143−4 4 VP (4)
2−Channel, 5−Lead SOT23−5 Package (CM1213A−02SO) Pin 1 2 3 4 5 Name NC VN CH1 CH2 VP Type − GND I/O I/O PWR Description No Connect Negative voltage supply rail ESD Channel ESD Channel Positive voltage supply rail
Top View NC (1) VN (2) CH1 (3) 1 D233 4 CH2 (4) 2 3 5 VP (5)
5−Lead SOT23−5
4−Channel, 6−Lead SOT23−6 (CM1213A−04SO) and SC70−6 (CM1213A−04s7) Pin 1 2 3 4 5 6 Name CH1 VN CH2 CH3 VP CH4 Type I/O GND I/O I/O PWR I/O Description ESD Channel Negative voltage supply rail ESD Channel ESD Channel Positive voltage supply rail ESD Channel Top View 4−Channel, 10−Lead MSOP−10 Package (CM1213A04MR) Pin 1 2 3 4 5 6 7 8 9 10 Name CH1 NC VP CH2 NC CH3 NC VN CH4 NC Type I/O − PWR I/O − I/O − GND I/O − Description ESD Channel No Connect Positive voltage supply rail ESD Channel No Connect ESD Channel No Connect Negative voltage supply rail ESD Channel No Connect CH1 NC VP CH2 NC Top View 1 2 3 4 5 10 9 8 7 6 NC CH4 VN NC CH3 D237 CH1 VN CH2 1 D234 2 3 6 5 4 CH4 VP CH3 CH1 VN CH2 Top View 1 D38 2 3 6 5 4 CH4 VP CH3
6−Lead SC70−6
6−Lead SOT23−6
10−Lead MSOP−10
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CM1213A
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter Operating Supply Voltage (VP − VN) Operating Temperature Range Storage Temperature Range DC Voltage at any channel input Rating 6.0 –40 to +85 –65 to +150 (VN − 0.5) to (VP + 0.5) Units V °C °C V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter Operating Temperature Range Package Power Rating SOT23−3, SOT143−4, SOT23−5, SOT23−6, and SC70−6 Packages MSOP−10 Package Rating –40 to +85 225 400 Units °C mW
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note1)
Symbol VP IP VF Parameter Operating Supply Voltage (VP−VN) Operating Supply Current Diode Forward Voltage Top Diode Bottom Diode Channel Leakage Current Channel Input Capacitance Channel Input Capacitance Matching ESD Protection − Peak Discharge Voltage at any channel input, in system Contact discharge per IEC 61000−4−2 standard Channel Clamp Voltage Positive Transients Negative Transients Dynamic Resistance Positive Transients Negative Transients (VP−VN) = 3.3 V IF = 8 mA; TA = 25°C 0.60 0.60 0.80 0.80 0.1 0.85 0.02 Conditions Min Typ 3.3 Max 5.5 8.0 0.95 0.95 1.0 1.2 Units V mA V
ILEAK CIN DCIN VESD
TA = 25°C; VP = 5 V, VN = 0 V At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V (Note 2) At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V (Note 2)
mA pF pF kV
TA = 25°C (Notes 2, 3, and 4) TA = 25°C, IPP = 1A, tP = 8/20 mS (Notes 2 and 4) IPP = 1A, tP = 8/20 mS Any I/O pin to Ground (Notes 2 and 4)
8 +10 –1.7 0.9 0.5 V
VCL
RDYN
W
1. All parameters specified at TA = –40°C to +85°C unless otherwise noted. 2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded. 3. These measurements performed with no external capacitor on VP (VP floating).
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CM1213A
PERFORMANCE INFORMATION Input Channel Capacitance Performance Curves
Figure 1. Typical Variation of CIN vs. VIN (f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN, 255C)
Figure 2. Typical Variation of CIN vs. Temp (f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN)
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CM1213A
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment)
Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP=3.3 V)
Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP=3.3 V)
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CM1213A
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the line being protected is: VCL = Fwd Voltage Drop of D1 + VSUPPLY + L1 x d(IESD) / dt + L2 x d(IESD) / dt where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can be approximated by DIESD/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V increment in VCL! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. The CM1213A has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip capacitor be connected between VP and the ground plane. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Note “Design Considerations for ESD Protection”, in the Applications section.
L2 VP
POSITIVE SUPPLY RAIL
VCC
PATH OF ESD CURRENT PULSE IESO
D1
L1 CHANNEL INPUT
25 A 0A
0.22 mF
LINE BEING PROTECTED
ONE CHANNEL D2 OF CM1213
VCL
VN
GROUND RAIL
Figure 5. Application of Positive ESD Pulse between Input Channel and Ground
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ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ
SYSTEM OR CIRCUITRY
ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ
BEING PROTECTED
CHASSIS GROUND
CM1213A
PACKAGE DIMENSIONS
SOT−23 3−Lead CASE 527AG−01 ISSUE O
D 3
SYMBOL A A1 b c E1 E D E E1 e
MIN 0.89 0.013 0.37 0.085 2.80 2.10 1.20
NOM
MAX 1.12 0.10 0.50 0.18 3.04 2.64 1.40
0.95 BSC 1.90 BSC 0.40 REF 0.54 REF
1 e e1 TOP VIEW
2
e1 L L1
θ
0º
8º
A
q
b A1
L1
L
c
SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC TO-236.
END VIEW
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CM1213A
PACKAGE DIMENSIONS
SOT−143, 4 Lead CASE 527AF−01 ISSUE A
SYMBOL A D e A1 A2 b 4 3 b2 c D E1 E E E1 1 2 e e1 e1 b L L1 L2 TOP VIEW 0.40 MIN 0.80 0.05 0.75 0.30 0.76 0.08 2.80 2.10 1.20 1.30 1.92 BSC 0.20 BSC 0.50 0.54 REF 0.25 0.60 2.90 0.90 NOM MAX 1.22 0.15 1.07 0.50 0.89 0.20 3.04 2.64 1.40
θ
0°
8°
A2
A
q
c
L2
b2 A1
L L1
SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC TO-253.
END VIEW
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CM1213A
PACKAGE DIMENSIONS
SOT−23, 5 Lead CASE 527AH−01 ISSUE O
D SYMBOL A A1 A2 b E1 E c D E E1 e e PIN #1 IDENTIFICATION TOP VIEW L L1 L2 0.30 MIN 0.90 0.00 0.90 0.30 0.08 2.90 BSC 2.80 BSC 1.60 BSC 0.95 BSC 0.45 0.60 REF 0.25 REF 0.60 1.15 NOM MAX 1.45 0.15 1.30 0.50 0.22
θ θ1 θ2
0° 5° 5°
4° 10° 10°
8° 15° 15°
θ1
A2
A
θ
b
θ2
SIDE VIEW
A1
L1
L2
L
c
END VIEW
Notes: (1) All dimensions in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-178.
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CM1213A
PACKAGE DIMENSIONS
SOT−23, 6 Lead CASE 527AJ−01 ISSUE A
D A B
6 5 2 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DATUM C IS THE SEATING PLANE.
E
1 3
E
L2
GAGE PLANE
e TOP VIEW
6X
b 0.20
L
M
SEATING PLANE
CA
S
B
S
DETAIL A
A2 A
6X
DIM A A1 A2 b c D E E1 e L L2
MILLIMETERS MIN MAX --1.45 0.00 0.15 0.90 1.30 0.20 0.50 0.08 0.26 2.70 3.00 2.50 3.10 1.30 1.80 0.95 BSC 0.20 0.60 0.25 BSC
c
DETAIL A
0.10 C A1 SIDE VIEW C
SEATING PLANE
END VIEW
RECOMMENDED SOLDERING FOOTPRINT*
3.30
0.85
6X
6X
0.56
0.95 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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CM1213A
PACKAGE DIMENSIONS
SC−88 (SC−70 6 Lead), 1.25x2 CASE 419AD−01 ISSUE A
SYMBOL D e e A A1 A2 b c E1 E D E E1 e L L1 TOP VIEW L2
MIN 0.80 0.00 0.80 0.15 0.10 1.80 1.80 1.15 0.26
NOM
MAX 1.10 0.10 1.00 0.30 0.18
2.00 2.10 1.25 0.65 BSC 0.36 0.42 REF 0.15 BSC
2.20 2.40 1.35 0.46
θ θ1
0º 4º
8º 10º
q1
A2 A q L L1
q1
b
A1
c END VIEW
L2
SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-203.
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CM1213A
PACKAGE DIMENSIONS
MSOP 10, 3x3 CASE 846AE−01 ISSUE O
SYMBOL A A1 A2 b c D E E1 E E1 e L L1 L2 0.40 0.00 0.75 0.17 0.13 2.90 4.75 2.90 3.00 4.90 3.00 0.50 BSC 0.60 0.95 REF 0.25 BSC 0.80 0.05 0.85 MIN NOM MAX 1.10 0.15 0.95 0.27 0.23 3.10 5.05 3.10
θ
0º
8º
DETAIL A
TOP VIEW D
A
A2
END VIEW c
A1
e SIDE VIEW
b
q L2
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187.
L L1 DETAIL A
FireWire is a registered trademark of Apple Computer, Inc. iLink is a trademark of S. J. Electro Systems, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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CM1213A/D
