CM1443-04CP
4-Channel EMI Filter Array
with ESD Protection
Features
• Four Channels of EMI Filtering for Data Ports
• Pi−Style EMI Filters in a Capacitor−Resistor−Capacitor (C−R−C)
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• ±15 kV ESD Protection on Each Channel
•
•
•
•
•
(IEC 61000−4−2 Level 4, Contact Discharge)
±30 kV ESD Protection on Each Channel (HBM)
Chip Scale Package (CSP) Features Extremely Low Lead Inductance
for Optimum Filter and ESD Performance
10−Bump; 0.4 mm Pitch, 1.560 x 1.053 mm Footprint
OptiGuardt Coating for Improved Reliability at Assembly
These Devices are Pb−Free and are RoHS Compliant
WLCSP10
CP SUFFIX
CASE 567BH
MARKING DIAGRAM
Applications
•
•
•
•
•
•
EMI Filtering and ESD Protection for Both Data and I/O Ports
Wireless Handsets
Handheld PCs / PDAs
MP3 Players
Notebooks
Desktop PCs
R = 100 W
8.5 pF
CS
8.5 pF
43
= CM1443−04CP
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
BLOCK DIAGRAM
FILTERn*
(Pins A1−A4)
43 MG
G
FILTERn*
(Pins C1−C4)
CS
GND
(Pins B1−B2)
Device
Package
Shipping†
CM1443−04CP
CSP−10
(Pb−Free)
3500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1 of 4 EMI/RFI + ESD Channels
*See Package/Pinout Diagrams for expanded pin information.
© Semiconductor Components Industries, LLC, 2011
March, 2011 − Rev. 3
1
Publication Order Number:
CM1443−04CP/D
CM1443−04CP
PACKAGE / PINOUT DIAGRAMS
Table 1. PIN DESCRIPTIONS
10−bump CSP Package
Pin(s)
Name
A1
FILTER1
Filter Channel 1
A2
FILTER2
Filter Channel 2
A3
FILTER3
Filter Channel 3
A4
FILTER4
Filter Channel 4
B1−B2
GND
Device Ground
C1
FILTER1
Filter Channel 1
C2
FILTER2
Filter Channel 2
C3
FILTER3
Filter Channel 3
C4
FILTER4
Filter Channel 4
Orientation
Marking
Description
A
1
+
Top View
(Bumps Down View)
2
3
4
43
B
C
Bottom View
(Bumps Up View)
FILTER1 FILTER2 FILTER3 FILTER4
C1
C2
C3
C4
GND
GND
B1
B2
FILTER1 FILTER2 FILTER3 FILTER4
A1
A2
A3
A4
A1
Orientation
Marking
CM1443−04CP
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
–65 to +150
°C
DC Power per Resistor
100
mW
DC Package Power Rating
600
mW
Storage Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
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2
Rating
Units
–40 to +85
°C
CM1443−04CP
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Conditions
R
Resistance
CT
Total Capacitance
At 2.5 V DC
CS
Single Capacitor
At 2.5 V DC
Diode Voltage (reverse bias)
IDIODE = 10 mA
ILEAK
Diode Leakage Current (reverse bias)
VDIODE = 3.3 V
VSIG
Signal Voltage
Positive Clamp
Negative Clamp
ILOAD = 10 mA
VESD
In−system ESD Withstand Voltage
a) Human Body Model, MIL−STD−883,
Method 3015
b) Contact Discharge per IEC 61000−4−2
Level 4
(Notes 2 and 4)
Clamping Voltage during ESD Discharge
MIL−STD−883 (Method 3015), 8 kV
Positive Transients
Negative Transients
(Notes 2, 3 and 4)
Cut−off Frequency
ZSOURCE = 50 W, ZLOAD = 50 W
R = 100 W, CS = 8.5 pF
VDIODE
VCL
fC
Min
Typ
Max
Units
80
100
120
W
14
17
21
pF
8.5
pF
5.5
5.6
−0.4
V
0.1
1.0
6.8
–0.8
9.0
−1.5
mA
V
kV
±30
±15
V
+10
–5
220
MHz
1. TA = 25°C unless otherwise specified.
2. ESD applied to input and output pins with respect to GND, one at a time.
3. Clamping voltage is measured at the opposite side of the EMI filter to the ESD pin. For example, if ESD is applied to Pin A1, then clamping
voltage is measured at Pin C1.
4. Unused pins are left open.
APPLICATION INFORMATION
Refer to Application Note “The Chip Scale Package”, for a detailed description of Chip Scale Packages offered by
ON Semiconductor.
PERFORMANCE INFORMATION
Figure 1. Resistance vs. Temperature
(normalized to resistance at 255C)
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3
CM1443−04CP
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (TA = 255C, DC Bias = 0 V, 50 W Environment)
Figure 2. Insertion Loss vs. Frequency (A1−C1 to GND B1)
Figure 3. Insertion Loss vs. Frequency (A2−C2 to GND B1)
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4
CM1443−04CP
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (TA = 255C, DC Bias = 0 V, 50 W Environment)
Figure 4. Insertion Loss vs. Frequency (A3−C3 to GND B2)
Figure 5. Insertion Loss vs. Frequency (A4−C4 to GND B2)
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5
CM1443−04CP
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (TA = 255C, DC Bias = 0 V, 50 W Environment)
Figure 6. Comparison of Filter Response Curves for CM1443 vs. DC Bias
Figure 7. Filter Capacitance vs. Input Voltage over Temperature
(normalized to capacitance at 2.5 VDC and 255C)
OptiGuardt is a trademark of Semiconductor Components Industries, LLC.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP10, 1.56x1.05
CASE 567BH−01
ISSUE O
SCALE 4:1
È
È
PIN A1
REFERENCE
2X
0.05 C
2X
0.05 C
D
A
DATE 26 JUL 2010
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
E
DIM
A
A1
A2
b
D
E
eD
eE
TOP VIEW
A2
OptiGuard Option
ÉÉÉÉ
0.05 C
A
RECOMMENDED
SOLDERING FOOTPRINT*
0.05 C
NOTE 3
A1
C
SIDE VIEW
eD/2
10X
b
0.05 C A B
0.03 C
eD
eE
B
A1
PACKAGE
OUTLINE
0.35
0.40
PITCH
10X
0.25
DIMENSIONS: MILLIMETERS
A
1 2 3
4 5 6
BOTTOM VIEW
DESCRIPTION:
SEATING
PLANE
0.35
C
DOCUMENT NUMBER:
MILLIMETERS
MIN
MAX
0.69
0.54
0.17
0.24
0.42 REF
0.24
0.29
1.56 BSC
1.05 BSC
0.400 BSC
0.347 BSC
98AON49817E
WLCSP10, 1.56X1.05
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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