CM2006
Praetorian) L-C LCD and
Camera EMI Filter Array
with ESD Protection
Product Description
The CM2006 connects between the VGA or DVI−I port connector
and the internal analog or digital flat panel controller logic. The
CM2006 incorporates ESD protection for all signals, level shifting for
the DDC signals and buffering for the SYNC signals. ESD protection
for the video, DDC and SYNC lines is implemented with
low−capacitance current steering diodes.
All connector interface pins are designed to safely handle the high
current spikes specified by IEC−61000−4−2 Level 4 (±8 kV contact
discharge). The ESD protection for the DDC, SYNC and VIDEO
signal pins is designed to prevent “backdrive current” when the device
is powered down while connected to a video source that is powered up.
Separate positive supply rails are provided for the VIDEO / SYNC
signals and DDC signals to facilitate interfacing with low voltage
video controller ICs and microcontrollers to provide design flexibility
in multi−supply−voltage environments.
Two Schmitt−triggered non−inverting buffers redrive and condition
the HSYNC and VSYNC signals from the video connector (SYNC1,
SYNC2). These buffers accept VESA VSIS compliant TTL input
signals and convert them to CMOS output levels that swing between
ground and VCC.
Two N−channel MOSFETs provide the level shifting function
required when the DDC controller or EDID EEPROM is operated at a
lower supply voltage than the monitor. The gate terminals for these
MOSFETS (VCC_DDC) should be connected to the supply rail
(typically 3.3 V, 2.5 V, etc.) that supplies power to the transceivers of
the DDC controller.
Features
• Includes ESD Protection, Level−Shifting, Buffering and Sync
•
•
•
•
•
•
Impedance Matching
VESA VSIS Version 1 Revision 2 Compatible Interface
Supports Optional NAVI Signalling Requirements
7 Channels of ESD Protection for all VGA Port
Connector Pins. All Pins Meet IEC−61000−4−2 Level 4
ESD Requirements (±8 kV Contact Discharge)
Very Low Loading Capacitance from ESD Protection
Diodes on VIDEO Lines (3 pF Maximum)
Schmitt−Triggered Input Buffers for HSYNC and
VSYNC Lines
These Devices are Pb−Free and are RoHS Compliant
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QSOP16
QR SUFFIX
CASE 492
MARKING DIAGRAM
CMDYYWW
CM2006
02QR
CM2006−02QR = Specific Device Code
YY
= Year
WW
= Work Week
ORDERING INFORMATION
Device
CM2006−02QR
Package
Shipping†
QSOP−16
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Bidirectional Level Shifting N−Channel FETs Provided
for DDC_CLK & DDC_DATA Channels
• Backdrive Protection on all Lines
• Compact 16−Lead QSOP Package
Applications
• VGA and DVI−I Ports in:
♦
♦
Monitors
TVs
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 4
1
Publication Order Number:
CM2006/D
CM2006
ELECTRICAL SCHEMATIC
VCC_DDC
VCC
BYP
1
8
11
7
VIDEO_1
VIDEO_2
VIDEO_3
GND
DDC_IN1
DDC_IN2
ENABLE
SYNC_IN1
SYNC_IN2
10
DDC_OUT1
DDC_OUT2
3
4
RT
RT
5
6
16
14
GND
9
SYNC_OUT2
SYNC_OUT1
12
2
13
15
PACKAGE / PINOUT DIAGRAM
Top View
VCC
1
16
SYNC_OUT2
ENABLE
2
15
SYNC_IN2
VIDEO_1
3
14
SYNC_OUT1
VIDEO_2
4
13
SYNC_IN1
VIDEO_3
5
12
DDC_IN2
GND
6
11
DDC_OUT2
VCC_DDC
7
10
DDC_OUT1
BYP
8
9
DDC_IN1
16 Pin QSOP
Table 1. PIN DESCRIPTIONS
Lead(s)
Name
Description
1
VCC
This is a supply input for the SYNC_1 and SYNC_2 level shifters, video protection and the DDC circuits.
2
ENABLE
Active high enable. Disables the Sync buffer outputs when low.
3
VIDEO_1
Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector.
4
VIDEO_2
Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector.
5
VIDEO_3
Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector.
6
GND
7
VCC_DDC
8
BYP
Ground reference supply pin.
This is an isolated supply input for the DDC_1 and DDC_2 level−shifting N−FET gates.
An external 0.22 mF bypass capacitor is required on this pin.
9
DDC_IN1
10
DDC_OUT1
DDC signal output. Connects to the monitor DDC logic.
11
DDC_OUT
DDC signal output. Connects to the monitor DDC logic.
12
DDC_IN2
DDC signal input. Connects to the video connector side of one of the DDC lines
13
SYNC_IN1
14
SYNC_OUT1
15
SYNC_IN2
16
SYNC_OUT2
DDC signal input. Connects to the video connector side of one of the DDC lines.signal output.
Sync signal buffer input. Connects to the video connector side of one of the sync lines.
Sync signal buffer output. Connects to the monitor SYNC logic.
Sync signal buffer input. Connects to the video connector side of one of the sync lines.
Sync signal buffer output. Connects to the monitor SYNC logic.
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2
CM2006
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
VCC_DDC and VCC Supply Voltage Inputs
DC Voltage at Inputs
VIDEO_1, VIDEO_2, VIDEO_3
DDC_IN1, DDC_IN2
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2, ENABLE
Rating
Units
[GND − 0.5] to +6.0
V
V
[GND − 0.5] to [VCC + 0.5]
[GND − 0.5] to 6.0
[GND − 0.5] to 6.0
[GND − 0.5] to [VCC + 0.5]
Operating Temperature Range
−40 to +85
°C
Storage Temperature Range
−40 to +150
°C
500
mW
Package Power Rating (TA = 25°C)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
VCC
Rating
Units
−40 to +85
°C
5
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
CM2006
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
ICC_DDC
ICC
Max
Units
VCC_DDC Supply Current
Parameter
VCC_DDC = 5.0 V
Conditions
10
mA
VCC Supply Current
VCC = 5 V; SYNC inputs at GND or VCC;
SYNC outputs unloaded
1
mA
VCC = 5 V; SYNC inputs at 3.0 V;
SYNC outputs unloaded
2.0
mA
1.0
V
VF
ESD Diode Forward Voltage
IF = 10 mA
VIH
Logic High Input Voltage
VCC = 5.0 V; (Note 2)
VIL
Logic Low Input Voltage
VCC = 5.0 V; (Note 2)
VHYS
Hysteresis Voltage
VCC = 5.0 V; (Note 2)
VOH
Logic High Output Voltage
IOH = 0 mA, VCC = 5.0 V; (Note 2)
VOL
Logic Low Output Voltage
IOL = 0 mA, VCC = 5.0 V; (Note 2)
SYNC Driver Output Resistance
VCC = 5.0 V; SYNC Inputs at GND or 3.0 V
Input Current
VIDEO Inputs
ROUT
IIN
IOFF
IBACKDRIVE
VON
CIN_VID
Min
Typ
2.0
V
0.5
400
V
mV
4.0
V
0.15
V
24
W
VCC = 5.0 V; VIN = VCC or GND
±10
mA
SYNC_IN1, SYNC_IN2 Inputs
VCC = 5.0 V; VIN = VCC or GND
±10
mA
Level Shifting N−MOSFET “OFF” State
Leakage Current
(VCC_DDC − VDDC_IN) < 0.4 V;
VDDC_OUT = VCC_DDC
10
mA
(VCC_DDC − VDDC_OUT) < 0.4 V;
VDDC_IN = VCC_DDC
10
mA
Current conducted from input pins when
Vcc is powered down.
VCC < VINPUT_PIN; (Note 5)
Voltage Drop Across Level−shifting
N−MOSFET when ”ON”
VCC_DDC = 2.5 V; VS = GND; IDS = 3 mA
VIDEO Input Capacitance
7
15
mA
10
0.18
V
VCC = 5.0 V; VIN = 2.5 V; f = 1 MHz
3
pF
VCC = 2.5 V; VIN = 1.25 V; f = 1 MHz
3.5
pF
tPLH
SYNC Driver L => H Propagation Delay
CL = 50 pF; VCC = 5.0 V; Input tR and tF < 5 ns
12
ns
tPHL
SYNC Driver H => L Propagation Delay
CL = 50 pF; VCC = 5.0 V; Input tR and tF < 5 ns
12
ns
tR, tF
SYNC Driver Output Rise & Fall Times
CL = 50 pF; VCC = 5.0 V; Input tR and tF < 5 ns
VESD1
ESD Withstand Voltage, Sync_out pins
only
VCC = 5 V; (Notes 3 and 4)
±2
kV
VESD
ESD Withstand Voltage
VCC = 5 V; (Notes 3 and 5)
±8
kV
3
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. All parameters specified over standard operating conditions unless otherwise noted.
2. These parameters apply only to the SYNC drivers. Note that ROUT = RT + RBUFFER.
3. Per the IEC−61000−4−2 International ESD Standard, Level 4 contact discharge method. BYP and VCC must be bypassed to GND via a low
impedance ground plane with a 0.22 mF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the
applicable pins and GND. ESD pulses can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3,
SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2. All pins are ESD protected to the industry standard ±2 kV Human Body Model
(MIL−STD−883, Method 3015).
4. This specification applies to the SYNC_OUT pins only.
5. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2.
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4
CM2006
APPLICATION INFORMATION
Figure 1. Typical Application Connection Diagram
NOTES:
1. The CM2006 should be placed as close to the VGA or DVI−I connector as possible.
2. The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B
signals.
3. If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with
external 37.5 W resistors.
4. “VF” are external video filters for the RGB signals.
5. Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins.
Connections to the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than
5 mm) for best ESD protection.
6. The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum
ESD withstand voltage at the DDC_OUT pins from ±8 kV to ±2 kV. If 8 kV ESD protection is required, a 0.22 mF
ceramic bypass capacitor should be connected between BYP and ground.
7. The SYNC buffers may be used interchangeably between HSYNC and VSYNC.
8. The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference
only. The component values and filter configuration may be changed to suit the application.
9. The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and
DDCA_DATA.
10. R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when
no VGA card is connected to the VGA monitor. If used, it should be noted that “back current” may flow between the
DDC pins and VCC_5V via these resistors when VCC_5V is powered down.
Praetorian® is a registered trademark of Semiconductor Components Industries, LLC.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QSOP16
CASE 492−01
ISSUE A
DATE 23 MAR 2011
2X
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT EX
CEED 0.005 PER SIDE. DIMENSION E1 DOES NOT
INCLUDE INTERLEAD FLASH OR PROTRUSION. IN
TERLEAD FLASH OR PROTRUSION SHALL NOT EX
CEED 0.005 PER SIDE. D AND E1 ARE DETERMINED
AT DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
0.20 C D
D
16
L2
D
A
9
GAUGE
PLANE
SEATING
PLANE
E
E1
C
L
C
DETAIL A
2X
2X 10 TIPS
0.20 C D
1
8
16X
e
B
b
0.25
A2
0.10 C
0.10 C
A1
16X
C
0.25 C D
M
C A-B D
h x 45 _
A
SEATING
PLANE
M
1.12
9
XXXXXXX
XXXXXXX
YYWWG
6.40
1
8
0.635
PITCH
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
1.24
---0.20
0.30
0.19
0.25
4.89 BSC
6.00 BSC
3.90 BSC
0.635 BSC
0.22
0.50
0.40
1.27
0.25 BSC
0_
8_
16X
0.42
16
DETAIL A
INCHES
MIN
MAX
0.053
0.069
0.004
0.010
0.049
---0.008
0.012
0.007
0.010
0.193 BSC
0.237 BSC
0.154 BSC
0.025 BSC
0.009
0.020
0.016
0.050
0.010 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
16X
H
DIM
A
A1
A2
b
c
D
E
E1
e
h
L
L2
M
XXXXX
YY
WW
G
= Specific Device Code
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
DIMENSIONS: MILLIMETERS
98AON04472D
QSOP16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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