CS51031
Fast P−Ch FET
Buck Controller
The CS51031 is a switching controller for use in DC−DC
converters. It can be used in the buck topology with a minimum
number of external components. The CS51031 consists of a VCC
monitor for controlling the state of the device, 1.0 A power driver for
controlling the gate of a discrete P−Channel transistor, fixed frequency
oscillator, short circuit protection timer, programmable Soft−Start,
precision reference, fast output voltage monitoring comparator, and
output stage driver logic with latch.
The high frequency oscillator allows the use of small inductors and
output capacitors, minimizing PC board area and systems cost. The
programmable Soft−Start reduces current surges at startup. The short
circuit protection timer significantly reduces the duty cycle to
approximately 1/30 of its cycle during short circuit conditions.
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8
1
SOIC−8
D SUFFIX
CASE 751
Features
•
•
•
•
•
•
•
•
•
1.0 A Totem Pole Output Driver
High Speed Oscillator (700 kHz max)
No Stability Compensation Required
Lossless Short Circuit Protection
VCC Monitor
2.0% Precision Reference
Programmable Soft−Start
Wide Ambient Temperature Range:
♦ Industrial Grade: −40°C to 85°C
♦ Commercial Grade: 0°C to 70°C
Pb−Free Packages are Available
MARKING DIAGRAM
8
51031
ALYWx
G
1
51031
A
L
Y
W
x
5.0 V−12 V
CIN
47 mF
MP1
IRF7416
VGATE
VGATE
COSC
470 pF
GND
CS51031
COSC
Device Code
Assembly Location
Wafer Lot
Year
Work Week
Continuation of Device Code
x = Y or G
= Pb−Free Package
MBRS360
VC
PIN CONNECTIONS
D1
PGND
G
=
=
=
=
=
=
CS
RVCC
100 W
VCC
CVCC
0.1 mF
CS
0.1 mF
VGATE
L
4.7 mH
RB
VFB
2.5 kW
RA
1.5 kW
CRR
0.1 mF
1
VC
PGND
CS
COSC
GND
VCC
VFB
VO
3.3 V @ 3 A
ORDERING INFORMATION
CO
100 mF × 2
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Figure 1. Typical Application Diagram
© Semiconductor Components Industries, LLC, 2005
October, 2005 − Rev. 11
1
Publication Order Number:
CS51031/D
CS51031
ORDERING INFORMATION
Operating
Temperature Range
Device
CS51031YD8
CS51031YD8G
−40°C < TA < 85°C
CS51031YDR8
CS51031YDR8G
CS51031GD8
CS51031GD8G
0°C < TA < 70°C
CS51031GDR8
CS51031GDR8G
Package
Shipping †
SOIC−8
98 Units / Rail
SOIC−8
(Pb−Free)
98 Units / Rail
SOIC−8
2500 / Tape & Reel
SOIC−8
(Pb−Free)
2500 / Tape & Reel
SOIC−8
98 Units / Rail
SOIC−8
(Pb−Free)
98 Units / Rail
SOIC−8
2500 / Tape & Reel
SOIC−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS
Value
Unit
Power Supply Voltage, VCC
Rating
20
V
Driver Supply Voltage, VC
20
V
Driver Output Voltage, VGATE
20
V
COSC, CS, VFB (Logic Pins)
6.0
V
Peak Output Current
1.0
A
Steady State Output Current
200
mA
Operating Junction Temperature, TJ
150
°C
Operating Temperature Range, TA
−40 to 85
°C
Storage Temperature Range, TS
−65 to 150
°C
2.0
kV
260 peak
230 peak
°C
°C
ESD (Human Body Model)
Lead Temperature Soldering:
Wave Solder: (through hole styles only) (Note 1)
Reflow (SMD styles only) (Note 2)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 10 sec. maximum.
2. 60 sec. max above 183°C.
PACKAGE LEAD DESCRIPTION
Package Pin Number
Pin Symbol
Function
1
VGATE
Driver pin to gate of external P−Ch FET.
2
PGND
Output power stage ground connection.
3
COSC
Oscillator frequency programming capacitor.
4
GND
Logic ground.
5
VFB
Feedback voltage input.
6
VCC
Logic supply voltage.
7
CS
Soft−Start and fault timing capacitor.
8
VC
Driver supply voltage.
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2
CS51031
ELECTRICAL CHARACTERISTICS (Specifications apply for 4.5 ≤ VCC ≤ 16 V, 3.0 V ≤ VC ≤ 16 V;
Industrial Grade: −40°C < TA < 85°C; −40°C < TJ < 125°C: Commercial Grade: 0°C < TA < 70°C; 0°C < TJ < 125°C, unless otherwise specified.)
Test Conditions
Characteristic
Oscillator
Typ
Max
Unit
160
200
240
kHz
−
110
−
mA
VFB = 1.2 V
Frequency
COSC = 470 pF
Charge Current
1.4 V < VCOSC < 2.0 V
Discharge Current
2.7 V > VCOSC > 2.0 V
Maximum Duty Cycle
1 − (tOFF/tON)
Short Circuit Timer
Min
−
660
−
mA
80.0
83.3
−
%
175
264
325
mA
mA
VFB = 1.0 V; CS = 0.1 mF; VCOSC = 2.0 V
Charge Current
1.0 V < VCS < 2.0 V
Fast Discharge Current
2.55 V > VCS > 2.4 V
40
66
80
Slow Discharge Current
2.4 V > VCS > 1.5 V
4.0
6.0
10
mA
Start Fault Inhibit Time
0 V < VCS < 2.5 V
0.70
0.85
1.40
ms
Valid Fault Time
2.6 V > VCS > 2.4 V
0.2
0.3
0.45
ms
GATE Inhibit Time
2.4 V > VCS > 1.5 V
9.0
15
23
ms
−
2.5
3.1
4.6
%
−
Fault Duty Cycle
CS Comparator
VFB = 1.0 V
Fault Enable CS Voltage
−
2.5
−
V
Max CS Voltage
VFB = 1.5 V
−
2.6
−
V
Fault Detect Voltage
VCS when GATE goes high
−
2.4
−
V
Fault Inhibit Voltage
Minimum VCS
−
1.5
−
V
Hold Off Release Voltage
VFB = 0 V
Regulator Threshold Voltage Clamp
VCS = 1.5 V
VFB Comparators
0.4
0.7
1.0
V
0.725
0.866
1.035
V
VCOSC = VCS = 2.0 V
Regulator Threshold Voltage
TJ = 25°C (Note 3)
TJ = −40 to 125°C
1.225
1.210
1.250
1.250
1.275
1.290
V
V
Fault Threshold Voltage
TJ = 25°C (Note 3)
TJ = −40 to 125°C
1.12
1.10
1.15
1.15
1.17
1.19
V
V
Threshold Line Regulation
4.5 V ≤ VCC ≤ 16 V
−
6.0
15
mV
Input Bias Current
VFB = 0 V
−
1.0
4.0
mA
Voltage Tracking
(Regulator Threshold − Fault Threshold Voltage)
70
100
120
mV
−
4.0
20
mV
Input Hysteresis Voltage
Power Stage
−
VCC = VC = 10 V; VFB = 1.2 V
GATE DC Low Saturation Voltage
VCOSC = 1.0 V; 200 mA Sink
−
1.2
1.5
V
GATE DC High Saturation Voltage
VCOSC = 2.7 V; 200 mA Source; VC = VGATE
−
1.5
2.1
V
Rise Time
CGATE = 1.0 nF; 1.5 V < VGATE < 9.0 V
−
25
60
ns
Fall Time
CGATE = 1.0 nF; 9.0 V > VGATE > 1.5 V
−
25
60
ns
V
VCC Monitor
Turn−On Threshold
−
4.200
4.400
4.600
Turn−Off Threshold
−
4.085
4.300
4.515
V
Hysteresis
−
65
130
200
mV
Current Drain
ICC
4.5 V < VCC < 16 V, Gate switching
−
4.5
6.0
mA
IC
3.0 V < VC < 16 V, Gate non−switching
−
2.7
4.0
mA
Shutdown ICC
VCC = 4.0
−
500
900
mA
3. Guaranteed by design, not 100% tested in production.
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3
CS51031
VC
VREF
RG
IC
Oscillator
Comparator
VGATE
Flip−Flop
+
A1
−
COSC
7IC
G1
VGATE
Q
R
F2
2.5 V
−
−
+
−
+
VFB
Comparator
A6
+
0.7 V
−
+
+
−
VREF
3.3 V
−
Fault
Comp
+
G4
VREF = 3.3 V
1.15 V
CS Charge
Sense
Comparator
−
+
VCCOK
VCC
−
+
Hold Off
Comp
VCC
G3
A4
+
IT
CS
Comparator
+
A2
−
F1
2.5 V
2.4 V
2.3 V
Q
R
G5
−
+
−
+
1.5 V
−
+
IT
5
−
+
CS
IT
55
VFB
1.25 V
−
1.5 V
PGND
Q
S
G2
−
A3
+
Slow Discharge
Comparator
S
Q
Slow Discharge
Flip−Flop
GND
Figure 2. Block Diagram
CIRCUIT DESCRIPTION
THEORY OF OPERATION
duration of the charge time. The P−Ch FET gets turned off
and remains off during the oscillator’s discharge time with
the maximum duty cycle to 80%. It requires 7.0 mV typical,
and 20 mV maximum ripple on the VFB pin is required to
operate. This method of control does not require any loop
stability compensation.
Control Scheme
The CS51031 monitors the output voltage to determine
when to turn on the P−Ch FET. If VFB falls below the internal
reference voltage of 1.25 V during the oscillator’s charge
cycle, the P−Ch FET is turned on and remains on for the
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4
CS51031
Startup
comparator (A4) sets the VFB comparator reference to
1.25 V completing the startup cycle.
The CS51031 has an externally programmable Soft−Start
feature that allows the output voltage to come up slowly,
preventing voltage overshoot on the output.
At startup, the voltage on all pins is zero. As VCC rises, the
VC voltage along with the internal resistor RG keeps the
P−Ch FET off. As VCC and VC continue to rise, the oscillator
capacitor (COSC ) and the Soft−Start/Fault Timing capacitor
(CS) charges via internal current sources. COSC gets charged
by the current source IC and CS gets charged by the IT source
combination described by:
ICS + IT *
Lossless Short Circuit Protection
The CS51031 has “lossless” short circuit protection since
there is no current sense resistor required. When the voltage
at the CS pin (the fault timing capacitor voltage) reaches
2.5 V during startup, the fault timing circuitry is enabled by
A2. During normal operation the CS voltage is 2.6 V. During
a short circuit or a transient condition, the output voltage
moves lower and the voltage at VFB drops. If VFB drops
below 1.15 V, the output of the fault comparator goes high
and the CS51031 goes into a fast discharge mode. The fault
timing capacitor, CS, discharges to 2.4 V. If the VFB voltage
is still below 1.15 V when the CS pin reaches 2.4 V, a valid
fault condition has been detected. The slow discharge
comparator output goes high and enables gate G5 which sets
the slow discharge flip−flop. The VGATE flip−flop resets and
the output switch is turned off. The fault timing capacitor is
slowly discharged to 1.5 V. The CS51031 then enters a
normal startup routine. If the fault is still present when the
fault timing capacitor voltage reaches 2.5 V, the fast and
slow discharge cycles repeat as shown in figure 3.
If the VFB voltage is above 1.15 V when CS reaches 2.4 V
a fault condition is not detected, normal operation resumes
and CS charges back to 2.6 V. This reduces the chance of
erroneously detecting a load transient as a fault condition.
IT
I
ǒ55
) TǓ
5
The internal Holdoff Comparator ensures that the external
P−Ch FET is off until VCS > 0.7 V, preventing the GATE
flip−flop (F2) from being set. This allows the oscillator to
reach its operating frequency before enabling the drive
output. Soft−Start is obtained by clamping the VFB
comparator’s (A6) reference input to approximately 1/2 of
the voltage at the CS pin during startup, permitting the
control loop and the output voltage to slowly increase. Once
the CS pin charges above the Holdoff Comparator trip point
of 0.7 V, the low feedback to the VFB Comparator sets the
GATE flip−flop during COSC’s charge cycle. Once the
GATE flip−flop is set, VGATE goes low and turns on the
P−Ch FET. When VCS exceeds 2.3 V, the CS charge sense
2.6 V
VCS
S2
2.4 V
S2
S1
S3
S3
S1
2.5 V
S2
S1
S3
S3
1.5 V
0.7 V
0V
0V
TSTART
START
td1
NORMAL OPERATION
tFAULT
tRESTART
td2
FAULT
VGATE
1.25 V
1.15 V
VFB
Figure 3. Voltage on Start Capacitor (VGS), the Gate (VGATE), and in the
Feedback Loop (VFB), During Startup, Normal and Fault Conditions
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5
tFAULT
CS51031
Buck Regulator Operation
and R2 and the reference voltage VREF, the power transistor
Q1 switches on and current flows through the inductor to the
output. The inductor current rises at a rate determined by
(VIN − VOUT)/L. The duty cycle (or “on” time) for the
CS51031 is limited to 80%. If output voltage remains higher
than nominal during the entire COSC change time, the Q1
does not turn on, skipping the pulse.
A block diagram of a typical buck regulator is shown in
Figure 4. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
inductor current IL is zero and the output voltage is at its
nominal value. The current drawn by the load is supplied by
the output capacitor CO. When the voltage across CO drops
below the threshold established by the feedback resistors R1
L
Q1
VIN
R1
CIN
CO
D1
RLOAD
R2
Control
Feedback
Figure 4. Buck Regulator Block Diagram
APPLICATIONS INFORMATION
CS51031 DESIGN EXAMPLE
If VF = 0.60 V and VSAT = 0.60 V then the above equation
becomes:
Specifications 12 V to 5.0 V, 3.0 A Buck Controller
DMAX + 5.6 + 0.62
9.0
• VIN = 12 V ±20% (i.e. 14.4 V max, 12 V nom, 9.6 V
•
•
•
•
•
min)
VOUT = 5.0 V ±2%
IOUT = 0.3 A to 3.0 A
Output ripple voltage < 50 mV max
Efficiency > 80%
fSW = 200 kHz
DMIN + 5.6 + 0.40
13.8
2) Switching Frequency and On and Off Time
Calculations
Given that fSW = 200 kHz and DMAX = 0.80
T + 1.0 + 5.0 ms
fSW
1) Duty Cycle Estimates
Since the maximum duty cycle D, of the CS51031 is
limited to 80% min, it is necessary to estimate the duty cycle
for the various input conditions over the complete operating
range.
The duty cycle for a buck regulator operating in a
continuous conduction mode is given by:
D+
TON(max) + T
DMAX + 5.0 ms
TON(min) + T
DMIN + 5.0 ms
0.62 ^ 3.0 ms
0.40 ^ 2.0 ms
TOFF(max) + TON(min) + 5.0 ms * 2.0 ms + 3.0 ms
3) Oscillator Capacitor Selection
VOUT ) VF
VIN * VSAT
The switching frequency is set by COSC, whose value is
given by:
where:
VSAT = RDS(ON) × IOUT max and RDS(ON) is the value at
TJ 100°C.
COSC in pF +
ǒ
10)6
95
FSW
106
FSW 1 ) 3
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6
* ǒ30F
103
SW
Ǔ
2
Ǔ
CS51031
4) Inductor Selection
6) VFB Divider
ǒ
The inductor value is chosen for continuous mode
operation down to 0.3 Amps.
The ripple current DI = 2 × IOUTmin = 2 × 0.3 A = 0.6 A.
This is the minimum value of inductor to keep the ripple
current < 0.6 A during normal operation.
A smaller inductor will result in larger ripple current.
Ripple current at a minimum off time is:
Let R2 = 1.0 K
Rearranging the divider equation gives:
The core must not saturate with the maximum expected
current, here given by:
OUT * 1.0Ǔ + 1.0 kWǒ5.0 V * 1.0Ǔ + 3.0 kW
ǒV1.25
1.25
R1 + R2
IMAX + IOUT ) DIń2 + 3.0 A ) 0.4 Ań2 + 3.2 A
7) Divider Bypass Capacitor CRR
5) Output Capacitor
Since the feedback resistors divide the output voltage by
a factor of 4.0, i.e. 5.0 V/1.25 V = 4.0, it follows that the
output ripple is also divided by four. This would require that
the output ripple be at least 60 mV (4.0 × 15 mV) to trip the
feedback comparator. We use a capacitor CRR to act as an
AC short.
The ripple voltage frequency is equal to the switching
frequency so we choose CRR = 1.0 nF.
The output capacitor and the inductor form a low pass
filter. The output capacitor should have a low ESL and ESR.
Low impedance aluminum electrolytic, tantalum or organic
semiconductor capacitors are a good choice for an output
capacitor. Low impedance aluminum are less expensive.
Solid tantalum chip capacitors are available from a number
of suppliers and are the best choice for surface mount
applications.
The output capacitor limits the output ripple voltage. The
CS51031 needs a maximum of 20 mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50 mV peak−to−peak is given by:
DI
fSW
DV
+
8.0
(200
0.6 A
103Hz) (50
10*3 V)
8) Soft−Start and Fault Timing Capacitor CS
CS performs several important functions. First it provides
a delay time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly. Secondly
it disables the fault circuitry during startup, it also provides
Soft−Start by clamping the reference voltage during startup,
allowing it to rise slowly, and, finally it controls the hiccup
short circuit protection circuitry. This reduces the duty cycle
to approximately 0.035 during short circuit conditions.
An important consideration in calculating CS is that it’s
voltage does not reach 2.5 V (the voltage at which the fault
detect circuitry is enabled) before VFB reaches 1.15 V
otherwise the power supply will never start.
If the VFB pin reaches 1.15 V, the fault timing comparator
will discharge CS and the supply will not start. For the VFB
voltage to reach 1.15 V the output voltage must be at least
4 × 1.15 = 4.6 V.
If we choose an arbitrary startup time of 900 ms, the value
of CS is:
+ 7.5mF
The minimum ESR needed to limit the output voltage
ripple to 50 mV peak−to−peak is:
*3
ESR + DV + 50 10
+ 83 mW
DI
0.6 A
The output capacitor should be chosen so that its ESR is
less than 83 mW.
During the minimum off time, the ripple current is 0.4 A
and the output voltage ripple will be:
DV + ESR
Ǔ
5.0 V + R1 ) R2 + 5.0 KW
1.0 mA
(VOUT ) VF) TOFF(min)
5.6 V 2.0 ms
DI +
+
+ 0.4 A
LMIN
28 mH
8.0
ǒ
The input bias current to the comparator is 4.0 mA. The
resistor divider current should be considerably higher than
this to ensure that there is sufficient bias current. If we
choose the divider current to be at least 250 times the bias
current this permits a divider current of 1.0 mA and
simplifies the calculations.
(VOUT ) VD) TOFF(max)
5.6 V 3.0 ms
L min +
+
+ 28 mH
DI
0.6 A
C+
Ǔ
VOUT + 1.25 V R1 ) R2 + 1.25 V R1 ) 1.0
R2
R2
DI + 83m W
0.4 + 33 mV
tStartup + CS 2.5 V
ICharge
CS min +
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7
900 ms 264 mA
+ 950 nF ^ 0.1 mF
2.5 V
CS51031
The fault time is the sum of the slow discharge time the
fast discharge time and the recharge time. It is dominated by
the slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4 V to 1.5 V and is
given by:
(2.4 V * 1.5 V)
CS
tSlowDischarge(t) +
the VCC and VC pins. This capacitor must also ensure that
the VCC remains above the UVLO voltage in the event of an
output short circuit. A low ESR capacitor of at least 100 mF
is good. A ceramic surface mount capacitor should also be
connected between VCC and ground to filter high frequency
noise.
10) MOSFET Selection
IDischarge
The CS51031 drives a P−Channel MOSFET. The VGATE
pin swings from GND to VC. The type of P−Ch FET used
depends on the operating conditions but for input voltages
below 7.0 V a logic level FET should be used.
A P−Ch FET with a continuous drain current (ID) rating
greater than the maximum output current is required.
The Gate−to−Source voltage VGS and the Drain−to
Source Breakdown Voltage should be chosen based on the
input supply voltage.
The power dissipation due to the conduction losses is
given by:
where IDischarge is 6.0 mA typical.
tSlowDischarge(t) + CS
1.5
105
The fast discharge time occurs when a fault is first
detected. The CS capacitor is discharged from 2.5 V to 2.4 V.
tFastDischarge(t) +
CS
(2.5 V * 2.4 V)
IFastDischarge
where IFastDischarge is 66 mA typical.
tFastDischarge(t) + CS
1515
PD + IOUT2
The recharge time is the time for CS to charge from 1.5 V
to 2.5 V.
tCharge(t) +
CS
RDS(ON) is the value at TJ + 100°C
The power dissipation of the P−Ch FET due to the
switching losses is given by:
where ICharge is 264 mA typical.
3787
PD + 0.5
The fault time is given by:
tFault + CS
(3787 ) 1515 ) 1.5
tFault + CS
(1.55
10*6
1.55
VIN
IOUT
(t r)
fSW
where tr = Rise Time.
105)
11) Diode Selection
105)
The flyback or catch diode should be a Schottky diode
because of it’s fast switching ability and low forward voltage
drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should be
at least 20 V for this 12 V application.
The diode power dissipation is given by:
For this circuit
tFault + 0.1
D
where
(2.5 V * 1.5 V)
ICharge
tCharge(t) + CS
RDS(ON)
105 + 15.5 ms
A larger value of CS will increase the fault time out time
but will also increase the Soft−Start time.
PD + IOUT
9) Input Capacitor
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage on
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8
VD
(1.0 * D min)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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