CS52843ED8

CS52843 Current Mode PWM Control Circuit The CS52843 provides all the necessary features to implement off−line fixed frequency current−mode control with a minimum number of external components. The CS52843 incorporates a new precision temperature−controlled oscillator to minimize variations in frequency. An undervoltage lockout ensures that VREF is stabilized before the output stage is enabled. In the CS52843 turn on is at 8.4 V and turn off at 7.6 V. Other features include low start−up current, pulse−by−pulse current limiting, and a high−current totem pole output for driving capacitive loads, such as gate of a power MOSFET. The output is low in the off state, consistent with N−channel devices. http://onsemi.com 8 1 SO−8 D SUFFIX CASE 751 • • • • • • • • • Features Optimized for Off−Line Control Internally Temperature Compensated Oscillator VREF Stabilized before Output Stage is Enabled Very Low Start−Up Current 300 μA (typ) Pulse−by−Pulse Current Limiting Improved Undervoltage Lockout Double Pulse Suppression 2.0% 5.0 Volt Reference High Current Totem Pole Output 14 1 SO−14 D SUFFIX CASE 751A PIN CONNECTIONS AND MARKING DIAGRAMS COMP VFB Sense OSC 1 52843 ALYWX 1 CS52843 AWLYWW 14 VREF VCC VOUT GND COMP NC VFB NC Sense NC OSC A WL, L YY, Y WW, W VREF NC VCC VCC Pwr VOUT Pwr GND GND = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device CS52843ED8 CS52843EDR8 CS52843ED14 CS52843EDR14 Package SO−8 SO−8 SO−14 SO−14 Shipping 95 Units/Rail 2500 Tape & Reel 55 Units/Rail 2500 Tape & Reel © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 4 1 Publication Order Number: CS52843/D CS52843 VCC Undervoltage Lockout VCC VCC Pwr 34 V GND 8.4 V/7.6 V Set/ Reset 5.0 Volt Reference VREF Internal Bias VFB Error Amplifier R 2.50 V − Oscillator S R R Sense 1.0 V Current Sensing Comparator PWM Latch Pwr GND 2R + OSC COMP OUTPUT ENABLE R NOR VOUT Figure 1. Block Diagram MAXIMUM RATINGS* Rating Supply Voltage (ICC < 30 mA) Supply Voltage (Low Impedance Source) Output Current Output Energy (Capacitive Load) Analog Inputs (VFB, VSENSE) Error Amp Output Sink Current Lead Temperature Soldering: 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value Self Limiting 30 ±1.0 5.0 −0.3 to 5.5 10 230 peak Unit − V A μJ V mA °C http://onsemi.com 2 CS52843 ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 85°C; VCC = 15 V (Note 2.); RT = 680 Ω; CT = 0.022 μF for triangle mode, RT = 10 kΩ; CT = 3.3 nF sawtooth mode; unless otherwise specified.) Parameter Reference Section Output Voltage Line Regulation Load Regulation Temperature Stability Total Output Variation Output Noise Voltage Long Term Stability Output Short Circuit Oscillator Section Initial Accuracy Voltage Stability Temperature Stability Amplitude Discharge Current Error Amp Section Input Voltage Input Bias Current AVOL Unity Gain Bandwidth PSRR Output Sink Current Output Source Current VOUT HIGH VOUT LOW Current Sense Section Gain Maximum Input Signal PSRR Input Bias Current Delay to Output Notes 3 & 4. VCOMP = 5.0 V, Note 3. 12 ≤ VCC ≤ 25 V, Note 3. VSENSE = 0 V TJ = 25°C, Note 2. 2.85 0.9 − − − 3.0 1.0 70 −2.0 150 3.15 1.1 − −10 300 V/V V dB μA ns VCOMP = 2.5 V VFB = 0 V 2.0 ≤ VOUT ≤ 4.0 V Note 2. 12 ≤ VCC ≤ 25 V VFB = 2.7 V, VCOMP = 1.1 V VFB = 2.3 V, VCOMP = 5.0 V VFB = 2.3 V, RL = 15 kΩ to GND VFB = 2.7 V, RL = 15 kΩ to VREF 2.42 − 65 0.7 60 2.0 −0.5 5.0 − 2.50 −0.3 90 1.0 70 6.0 −0.8 6.0 0.7 2.58 −2.0 − − − − − − 1.1 V μA dB MHz dB mA mA V V Sawtooth Mode, TJ = 25°C, Note 2. Triangle Mode, TJ = 25°C 12 ≤ VCC ≤ 25 V Sawtooth Mode TMIN ≤ TA ≤ TMAX Triangle Mode TMIN ≤ TA ≤ TMAX, Note 2. VOSC (peak to peak) TJ = 25°C TMIN ≤ TA ≤ TMAX 47 44 − − − − 7.3 6.8 52 52 0.2 5.0 8.0 1.7 8.3 − 57 60 1.0 − − − 9.3 9.8 kHz kHz % % % V mA mA TJ = 25°C, IREF = 1.0 mA 12 ≤ VCC ≤ 25 V 1.0 ≤ IREF ≤ 20 mA Note 2. Line, Load, Temp. Note 2. 10 Hz ≤ f ≤ 10 kHz, TJ = 25°C, Note 2. TA = 125°C, 1000 Hrs. Note 2. TA = 25°C 4.9 − − − 4.82 − − −30 5.0 6.0 6.0 0.2 − 50 5.0 −100 5.1 20 25 0.4 5.18 − 25 −180 V mV mV mV/°C V μV mV mA Test Conditions Min Typ Max Unit 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at a trip point of latch with VFB = 0. 4. Gain defined as: A + DVCOMP ; 0 v VSENSE v 0.8 V DVSENSE http://onsemi.com 3 CS52843 ELECTRICAL CHARACTERISTICS (continued) (−40°C ≤ TA ≤ 85°C; VCC = 15 V (Note 2.); RT = 680 Ω; CT = 0.022 μF for triangle mode, RT = 10 kΩ; CT = 3.3 nF sawtooth mode; unless otherwise specified.) Parameter Output Section Output Low Level Output High Level Rise Time Fall Time Output Leakage Total Standby Current Start−Up Current Operating Supply Current VCC Zener Voltage Undervoltage Lockout Section Start Threshold − 7.8 7.0 8.4 7.6 9.0 8.2 V V − VFB = VSENSE = 0 V, RT = 10 kΩ; CT = 3.3 nF ICC = 25 mA − − − 300 11 34 500 17 − μA mA V ISINK = 20 mA ISINK = 200 mA ISOURCE = 20 mA ISOURCE = 200 mA TJ = 25°C, CL = 1.0 nF, Note 5. TJ = 25°C, CL = 1.0 nF, Note 5. UVLO Active VOUT = 0 − − 13 12 − − − 0.1 1.5 13.5 13.5 50 50 −0.01 0.4 2.2 − − 150 150 −10 V V V V ns ns μA Test Conditions Min Typ Max Unit Min. Operating Voltage After Turn On 5. These parameters, although guaranteed, are not 100% tested in production. PACKAGE PIN DESCRIPTION Package Lead Number SO−8 1 2 3 4 5 − 6 − 7 8 − SO−14 1 3 5 7 8 9 10 11 12 14 2, 4, 6, 13 Lead Symbol COMP VFB SENSE OSC GND Pwr GND VOUT VCCPwr VCC VREF NC Function Error amp output, used to compensate error amplifier. Error amp inverting input. Noninverting input to Current Sense Comparator. Oscillator timing network with capacitor to ground, resistor to VREF. Ground. Output driver ground. Output drive pin. Output driver positive supply. Positive power suppy. Output of 5.0 V internal reference. No Connection. http://onsemi.com 4 CS52843 TYPICAL PERFORMANCE CHARACTERISTICS 900 800 Duty Cycle (%) RT = 10 kΩ 700 Frequency (kHz) 600 500 400 300 200 100 .0005 .001 RT = 1.5 kΩ RT = 680 Ω 100 90 80 70 60 50 40 30 20 10 200 300 400 100 2k 5k 7k 10 k 3k .002 .003 CT (μF) .005 .01 .02 .03 .04 .05 500 700 1k 4k RT (Ω) Figure 2. Oscillator Frequency vs CT Figure 3. Oscillator Duty Cycle vs RT VREF RT 2N2222 4.7 kΩ 1.0 kΩ Error Amp Adjust 4.7 kΩ 5.0 kΩ Sense Adjust 100 kΩ COMP VREF 0.1 μF VFB Sense VCC 0.1 μF VOUT 1.0 kΩ 1.0 W VOUT A VCC OSC GND CT GND Figure 4. Test Circuit Open Loop Laboratory Test Fixture CIRCUIT DESCRIPTION http://onsemi.com 5 CS52843 VCC ON/OFF Command to reset of IC VON = 8.4 V VOFF = 7.6 V VOSC OSC RESET Toggle F/F Output EA Output Switch Current VCC ICC < 15 mA < 500 μA VON VOFF VCC Figure 5. Startup Voltage for the CS52843 Undervoltage Lockout IO VO During Undervoltage Lockout (Figure 5), the output driver is biased to sink minor amounts of current. The output should be shunted to ground with a resistor to prevent activating the power switch with extraneous leakage currents. PWM Waveform Figure 6. Timing Diagram Setting the Oscillator The times tc and td can be determined as follows: V * VLOWER tc + RTCT ln REF VREF * VUPPER VREF * IdRTVLOWER td + RTCT ln VREF * IdRT * VUPPER To generate the PWM waveform, the control voltage from the error amplifier is compared to a current sense signal which represents the peak output inductor current (Figure 6). An increase in VCC causes the inductor current slope to increase, thus reducing the duty cycle. This is an inherent feed−forward characteristic of current mode control, since the control voltage does not have to change during changes of input supply voltage. When the power supply sees a sudden large output current increase, the control voltage will increase allowing the duty cycle to momentarily increase. Since the duty cycle tends to exceed the maximum allowed to prevent transformer saturation in some power supplies, the internal oscillator waveform provides the maximum duty cycle clamp as programmed by the selection of oscillator timing components. Substituting in typical values for the parameters in the above formulas: VREF + 5.0 V, VUPPER + 2.7 V, VLOWER + 1.0 V, Id + 8.3 mA then tc [ 0.5534RTCT 2.3 * 0.0083RT td + RTCT ln 4.0 * 0.0083RT For better accuracy RT should be ≥ 10 kΩ. Grounding High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to GND in a single point ground. The transistor and 5.0 kΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Sense. http://onsemi.com 6 CS52843 VREF VIN OSC CT GND RT Large RT (≈ 10 kΩ) VOSC Internal Clock Sawtooth Mode Small RT (≈ 700 Ω) VREF VUPPER VLOWER tc td Internal Clock Triangular Mode Figure 7. Oscillator Timing Network and Parameters http://onsemi.com 7 CS52843 PACKAGE DIMENSIONS SO−8 DF SUFFIX CASE 751−07 ISSUE W −X− A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 S 4 0.25 (0.010) M Y M −Y− G K C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S SO−14 D SUFFIX CASE 751A−03 ISSUE F − A− 14 8 − B− 1 7 P 7 PL 0.25 (0.010) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C R X 45 _ F −T− SEATING PLANE D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 PACKAGE THERMAL DATA Parameter RΘJC RΘJA Typical Typical SO−8 45 165 SO−14 30 125 Unit °C/W °C/W http://onsemi.com 8 CS52843 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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