CS5308

CS5308 Two−Phase PWM Controller with Integrated Gate Drivers for VRM 8.5 The CS5308 is a second−generation, two−phase step down controller that incorporates all control functions required to power next generation processors. Proprietary multi−phase architecture guarantees balanced load current distribution and reduces overall solution cost in high current applications. Enhanced V2™ control architecture provides the fastest possible transient response, excellent overall regulation, and ease of use. The CS5308 is a second generation PWM controller because it optimizes transient response by combining traditional Enhanced V 2 w ith an internal PWM ramp and fast−feedback directly from VCORE to the internal PWM comparator. These enhancements provide greater design flexibility, facilitate use and reduce output voltage jitter. The multi−phase architecture reduces input and output filter ripple, allowing for a significant reduction in filter size and inductor values with a corresponding increase in the output inductor current slew rate. This approach allows a considerable reduction in input and output capacitor requirements, as well as reducing overall solution size and cost. The CS5308 includes VTT monitoring and timing, VTT Power Good (VTTPGD), Power Good (PWRGD), and internal MOSFET gate drivers to provide a “fully integrated solution” to simplify design, minimize circuit board area, and reduce overall system cost. Features • Enhanced V2 Control Method • Internal PWM Ramp • Fast−Feedback Directly from VCORE • 5−Bit DAC with 1% Tolerance • Adjustable Output Voltage Positioning • 200 kHz to 800 kHz Operation Set by Resistor • Current Sensed through Sense Resistors or Output Inductors • Adjustable Hiccup Mode Current Limit • Overvoltage Protection through Synchronous MOSFETs • Individual Current Limits for Each Phase • On−Board Current Share Amplifiers • 3.3 V, 1.0 mA Reference Output • VTT Monitoring and VTT Power Good (VTTPGD) • VCORE Power Good • On/Off Control (through COMP Pin) • Improved Noise Immunity http://onsemi.com MARKING DIAGRAM 28 1 SO−28L DW SUFFIX CASE 751F A WL, L YY, Y WW, W 28 CS5308 AWLYYWW 1 = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS COMP VFB VDRP REF ILIM VID25 VID0 VID1 VID2 VID3 PWRGD CSREF CS1 CS2 1 28 ROSC LGND VCCL VCCH1 GATE(H)1 GATE(L)1 PGND VCCL12 GATE(L)2 GATE(H)2 VCCH2 VTTPGD VTTCT VTT ORDERING INFORMATION Device CS5308GDW28 CS5308GDWR28 Package SO−28L SO−28L Shipping 27 Units/Rail 1000 Tape & Reel © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 6 1 Publication Order Number: CS5308/D CS5308 L1 300 nH +5.0 V +12 V RFBK1 6.49 k CFBK2 470 pF CAMP 3.9 nF RCMP1 5.62 k R5V 1.0 W CVCC 1.0 mF VFB RDRP1 11.5 k CCMP1 3.3 nF CCMP2 0.1 mF SIGGND ROSC 39.2 k COMP ROSC VFB LGND VDRP VCCL REF VCCH1 ILIM GATE(H)1 VID25 GATE(L)1 PGND VID0 VID1 VCCL12 VID2 GATE(L)2 VID3 GATE(H)2 VCCH2 PWRGD CSREF VTTPGD CS1 VTTCT CS2 VTT CS5308 VTT RCSREF 20 k CS REF CCSREF 0.01 mF SIGGND RCS1 100 k SIGGND GATE2 COUT Electrolytics + CQ1 0.1 mF Q1 GATE1 Q2 + CINPUT Electrolytics VOUT L2 825 nH RLIM1 5.76 k CREF 0.1 mF RLIM2 1.0 k SIGGND VID25 VID0 VID1 VID2 VID3 PWRGD CVCCH1 1.0 mF CQ3 0.1 mF CVCC12 1.0 mF GATE3 CVCCH2 1.0 mF CVTT 0.1 mF SIGGND RVTT 1.0 k GATE4 Q3 CCER Ceramics L3 825 nH Q4 CS1 CS2 CCS1 0.01 mF SWNODE1 SWNODE2 CCS2 0.01 mF RCS2 100 k Recommended Components: L1: Coiltronics CTX15−14771 or T30−26 core with 3T of #16 AWG L2: Coiltronics CTX22−15401 X1 or T50−52 with 5T of #16 AWG Bifilar CINPUT: 2 × Sanyo Oscon 6SP680M (680 mF, 6.3 V) COUT: 7 × Rubycon 6.3ZA1000M10x16 (1000 mF, 6.3 V) CCERAMICS: 12 × Panasonic ECJ−3YB0J106K (10 mF, 6.3 V) Q1−Q4: ON Semiconductor NTB85N03 (28 V, 85 A) Figure 1. Application Diagram. 5.0 V to 1.7 V at 28 A, 335 kHz with 12 V Bias for Pentium) III Applications http://onsemi.com 2 CS5308 MAXIMUM RATINGS* Rating Operating Junction Temperature Lead Temperature Soldering: Storage Temperature Range Package Thermal Resistance Junction−to−Case, RqJC Junction−to−Ambient, RqJA ESD Susceptibility (Human Body Model) JEDEC Moisture Sensitivity 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value 150 230 peak −65 to 150 15 75 2.0 Level 2 Unit °C °C °C °C/W °C/W kV − MAXIMUM RATINGS Pin Name COMP VFB VDRP CS1−CS2 CSREF PWRGD VID Pins ILIM REF VTT VTTCT VTTPGD VCCHx GATE(H)x GATE(L)x VCCL12 PGND LGND VCCL ROSC VMAX 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 20 V 20 V 16 V 16 V 0.3 V 0V 16 V 6.0 V VMIN −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V DC −2.0 V for 100 ns −0.3 V DC −2.0 V for 100 ns −0.3 V −0.3 V 0V −0.3 V −0.3 V ISOURCE 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA N/A 1.5 A for 1.0 ms, 200 mA DC 1.5 A for 1.0 ms, 200 mA DC N/A 2.0 A, 1.0 ms, 200 mA DC 50 mA N/A 1.0 mA ISINK 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 8.0 mA 1.0 mA 1.0 mA 20 mA 1.0 mA 40 mA 8.0 mA 1.5 A for 1.0 ms, 200 mA DC 1.5 A for 1.0 ms, 200 mA DC 1.5 A for 1.0 ms, 200 mA DC 1.5 A for 1.0 ms, 200 mA DC N/A N/A 50 mA 1.0 mA http://onsemi.com 3 CS5308 ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCCH1 = VCCH2 < 20 V; 4.5 V < VCCL =VCCL12 < 14 V; CGATE = 3.3 nF, RROSC = 32.4 k, CCOMP = 0.1 mF, CREF = 0.1 mF, DAC Code 01000 (1.65 V), CVCC = 0.1 mF; unless otherwise specified.) Characteristic Voltage Identification DAC Accuracy (all codes) VID25 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID3 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID2 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Measure VFB = COMP − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − VID25, VID3, VID2, VID1, VID0 VID25, VID3, VID2, VID1, VID0 − − − 1.039 1.064 1.089 1.114 1.139 1.163 1.188 1.213 1.238 1.262 1.287 1.312 1.337 1.361 1.386 1.411 1.436 1.460 1.485 1.510 1.535 1.559 1.584 1.609 1.634 1.658 1.683 1.708 1.733 1.757 1.782 1.807 1.00 25 3.15 − − 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.25 50 3.3 ± 1.0 − 1.061 1.086 1.111 1.136 1.162 1.187 1.212 1.237 1.263 1.288 1.313 1.338 1.364 1.389 1.414 1.439 1.465 1.490 1.515 1.540 1.566 1.591 1.616 1.641 1.667 1.692 1.717 1.742 1.768 1.793 1.818 1.843 1.5 100 3.45 % − V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V kW V Test Conditions Min Typ Max Unit Input Threshold Input Pull−up Resistance Pull−up Voltage http://onsemi.com 4 CS5308 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCCH1 = VCCH2 < 20 V; 4.5 V < VCCL =VCCL12 < 14 V; CGATE = 3.3 nF, RROSC = 32.4 k, CCOMP = 0.1 mF, CREF = 0.1 mF, DAC Code 01000 (1.65 V), CVCC = 0.1 mF; unless otherwise specified.) Characteristic Power Good Output Power Good Fault Delay PWRGD Low Voltage Output Leakage Current Lower Threshold Upper Threshold Voltage Feedback Error Amplifier VFB Bias Current, (Note 2.) COMP Source Current COMP Sink Current COMP Discharge Threshold Voltage Transconductance Output Impedance Open Loop DC Gain Unity Gain Bandwidth PSRR @ 1.0 kHz COMP Max Voltage COMP Min Voltage Hiccup Latch Discharge Current COMP Discharge Ratio PWM Comparators Minimum Pulse Width Channel Startup Offset CS1 = CS2 = CSREF V(CS1) = V(CS2) = V(VFB) = V(CSREF) = 0 V; Measure V(COMP) when GATE(H)1,2 switch high − 0.3 350 0.4 475 0.5 ns V Note 3. 0.01 mF − VFB = 1.6 V COMP Open VFB = 1.7 V COMP Open − − 0.9 V < VFB < 1.9 V COMP = 0.5 V to 2.0 V; VFB = 1.6 V COMP = 0.5 V to 2.0 V; VFB = 1.7 V Test Conditions Min Typ Max Unit CSREF = DAC to DAC ± 15% IPWRGD = 4.0 mA VPWRGD = 5.5 V − − 25 − − −15 9.0 50 250 0.1 −12 12 100 400 10 −9.0 15 ms mV mA % % 9.4 15 15 0.20 − − 60 − − 2.4 − 2.0 4.0 10.3 30 30 0.27 32 2.5 90 400 70 2.7 0.1 5.0 6.0 11.1 60 60 0.34 − − − − − − 0.2 10 10 mA mA mA V mmho MW dB kHz dB V V mA − − −10 mA < ICOMP < +10 mA − VTT Power Good VTT Threshold VTTPGD Low Voltage VTTPGD Leakage Current VTTCT Threshold Voltage VTTCT Charge Current VTTCT Discharge Threshold GATES High Voltage (AC) Low Voltage (AC) Rise Time GATEx Measure VCCx − GATEx, Note 3. Measure GATEx, Note 3. 1.0 V < GATE < 8.0 V; VCCx = 10 V − IVTTPGD = 4.0 mA VTTPGD = 5.5 V − Note 2. − 1.03 − − 1.0 15 0.24 1.05 0.25 0.1 1.05 30 0.32 1.07 0.4 10 1.10 45 0.38 V V mA V mA V − − − 0 0 35 1.0 0.5 80 V V ns 2. The VFB Bias Current and VTTCT Charge Currents change with the value of ROSC per Figure 4. 3. Guaranteed by design. Not tested in production. http://onsemi.com 5 CS5308 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCCH1 = VCCH2 < 20 V; 4.5 V < VCCL =VCCL12 < 14 V; CGATE = 3.3 nF, RROSC = 32.4 k, CCOMP = 0.1 mF, CREF = 0.1 mF, DAC Code 01000 (1.65 V), CVCC = 0.1 mF; unless otherwise specified.) Characteristic GATES Fall Time GATEx GATE(H)x to GATE(L)x Delay GATE(L)x to GATE(H)x Delay GATE Pull−down Oscillator Switching Frequency Switching Frequency Switching Frequency ROSC Voltage Phase Delay Adaptive Voltage Positioning VDRP Offset VDRP Operating Voltage Range Maximum VDRP Voltage CS1 = CS2 = CSREF, VFB = COMP, Measure VDRP − COMP Measure VDRP − GND, Note 4. (CS1 = CS2) − CSREF = 50 mV, VFB = COMP Measure VDRP − COMP − −15 0.1 260 − − 320 15 2.3 400 mV V mV Rising edge only ROSC = 32.4 k ROSC = 63.4 k, Note 4. ROSC = 16.2 k, Note 4. − 340 150 600 − 165 400 200 800 1.0 180 460 250 1000 − 195 kHz kHz kHz V deg 8.0 V > GATE > 1.0 V; VCCx = 10 V Test Conditions Min Typ Max Unit − 30 30 − 35 65 65 1.2 80 110 110 1.6 ns ns ns V GATE(H)x < 2.0 V, GATE(L)x > 2.0 V GATE(L)x < 2.0 V, GATE(H)x > 2.0 V Force 100 mA into Gate with no power applied to VCCHx and VCCLx = 2.0 V Current Share Amp to VDRP Gain Current Sensing and Sharing CS1 − CS2 Input Bias Current CSREF Input Bias Current Current Sense Amplifier Gain Current Sense Amp Mismatch (The sum of gain and offset errors.) Current Sense Input to ILIM Gain Current Limit Filter Slew Rate ILIM Operating Voltage Range ILIM Bias Current Single Phase Pulse by Pulse Current Limit: V(Cx) − V(CSREF) Current Sense Amplifier Bandwidth Note 4. 2.6 3.2 4.0 V/V V(Cx) = V(CSREF) = 0 V − − 0 < CSx − CSREF < 50 mV. Note 4. ILIM = 1.0 V Note 4. Note 4. 0 V < ILIM < 1.0 V − − − 3.05 −5.0 5.5 7.5 0.1 − 90 1.0 0.1 0.5 3.50 − 6.5 15 − 0.1 105 − 2.0 2.0 3.95 5.0 7.5 40 1.3 1.0 135 − mA mA V/V mV V/V mV/ms V mA mV MHz 4. Guaranteed by design. Not tested in production. http://onsemi.com 6 CS5308 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCCH1 = VCCH2 < 20 V; 4.5 V < VCCL =VCCL12 < 14 V; CGATE = 3.3 nF, RROSC = 32.4 k, CCOMP = 0.1 mF, CREF = 0.1 mF, DAC Code 01000 (1.65 V), CVCC = 0.1 mF; unless otherwise specified.) Characteristic General Electrical Specifications VCCL Operating Current VCCL12 Operating Current VCCH1 Operating Current VCCH2 Operating Current VCCL Start Threshold VCCL Stop Threshold VCCL Hysteresis VCCH1 Start Threshold VCCH1 Stop Threshold VCCH1 Hysteresis Reference Output VREF Output Voltage Internal Ramp Ramp Height @ 50% DTC CS1 = CS2 = CSREF − 125 − mV 0 mA < I(VREF) < 1.0 mA 3.2 3.3 3.4 V VFB = COMP (no switching) VFB = COMP (no switching) VFB = COMP (no switching) VFB = COMP (no switching) GATEs switching, COMP charging GATEs stop switching, COMP discharging GATEs not switching, COMP not charging GATEs switching, COMP charging GATEs stop switching, COMP discharging GATEs not switching, COMP not charging − − − − 4.05 3.75 100 8.0 7.5 300 20.5 8.0 2.8 2.5 4.3 4.1 200 8.5 8.0 500 26.0 11 4.0 3.5 4.5 4.35 300 9.0 8.5 700 mA mA mA mA V V mV V V mV Test Conditions Min Typ Max Unit 5. Guaranteed by design. Not tested in production. http://onsemi.com 7 CS5308 PACKAGE PIN DESCRIPTION PACKAGE PIN # 28 Lead SO Wide 1 2 PIN SYMBOL COMP VFB FUNCTION Output of the error amplifier and input for the PWM comparators. Voltage Feedback Pin. To use Adaptive Voltage Positioning, set the light load offset voltage by connecting a resistor between VFB and VOUT. The resistor and the VFB bias current determine the offset. For no adaptive positioning connect VFB directly to VOUT. Current sense output for Adaptive Voltage Positioning (AVP). The offset of this pin above the DAC voltage is proportional to the output current. Connect a resistor from this pin to VFB to set the amount of AVP or leave this pin open for no AVP. This pin’s maximum working voltage is 2.3 Vdc. Reference output. Decouple to LGND with 0.1 mF. Sets threshold for current limit. Connect to reference through a resistive divider. This pin’s maximum working voltage is 1.3 Vdc. Voltage ID DAC inputs. These pins are internally pulled up to 3.3 V if left open. Power Good Output. Open collector output goes low when CSREF is out of regulation. Reference for current sense amplifiers, input to the Power Good comparators, and fast feedback connection to the PWM comparator. Connect this pin to the output voltage through a resistor equal to 1/5th the value of the current sense resistors. The input voltage to this pin must not exceed the maximum VID (DAC) setting by more than 100 mV. Current Sense inputs. Connect Current Sense network for the corresponding phase to each input. The input voltages to these pins must be kept within 105 mV of CSREF or pulse− by−pulse current limit will be triggered. VTT sense input. The voltage on this pin must be higher than the VTT threshold (nominally 1.05 V) or switching will not occur. 1.0 ms timer for VTT Power Good. VTT Power Good output. Open collector, pulls down when VTT < 1.03 V. Power for channel 2 high side gate driver. High and low side gate drivers for channels 1 and 2. Power for both low side gate drivers. Return for all gate drivers. Low and high side gate drivers for channels 1 and 2. Power for channel 1 high side gate driver. Power for logic. UVLO Sense for supply connects to this pin. Ground for internal control circuits and the IC substrate connection. A resistor from this pin to ground sets operating frequency. 3 VDRP 4 5 REF ILIM 6−10 11 12 VID Pins PWRGD CSREF 13, 14 CS1−CS2 15 VTT 16 17 18 19, 20 21 22 23, 24 25 26 27 28 VTTCT VTTPGD VCCH2 GATE(H)2, GATE(L)2 VCCL12 PGND GATE(L)1, GATE(H)1 VCCH1 VCCL LGND ROSC http://onsemi.com 8 VTT IVTTCT VTTCT VCCH1 VCCH2 VTTPGD VCC VCCL12 PH1 0.32 V S VCCH1 Gate Non−Overlap VCCL VCCL VCCH1 + − S − START STOP − + + − 1.05 V S 1.0 V − VID0 + 4.3 V 4.1 V + VID3 S PWM1 DAC OUT FAULT SET DOMINANT OVIC CS5308 PWRGD 0.27 V + AVPA CSREF VITOTAL DAC*0.88 CSA1 − + × 0.91 AVPA CO1 1 2 IDCHG 1 2 FAULT FAULT CS1 + − × 3.50 CS2 DAC OUT + CO2 LGND VDRP COMP + EA − CSA2 − − + Figure 2. Block Diagram DAC*1.12 CO1 + − × 1.86 − PWM2 RESC CSREF − − DLY 50 ms + R RAMP 2 RESET DOMINANT http://onsemi.com − R COMP RAMP 1 R RESET DOMINANT 0.4 V + CO2 + − + VID2 − VID1 DAC − VTTPGD − 8.5 V 8.0 V R SET DOMINANT VID25 mV + R + RESET DOMINANT REF 3.3 V REF START STOP ILIM − GATE(H)1 + VCCL1 GATE(L)2 − + MAXC1 + + PH2 S VCCH2 PGND + − − + 9 − 0.4 V FAULT Gate Non−Overlap GATE(H)2 VCCL2 GATE(L)2 + MAXC2 − 0.4 V FAULT CURRENT SOURCE GEN PH1 PH2 DAC OUT IBIAS OSC RAMP 1 RAMP 2 VFB ROSC CS5308 TYPICAL PERFORMANCE CHARACTERISTICS 900 800 VFB Bias Current (mA) 700 Frequency (kHz) 600 500 400 300 200 100 10 20 30 40 50 ROSC Value (kW) 60 70 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 −50 10 20 30 50 60 70 ROSC Resistance (kW) 40 80 IVTTCT @ 25°C IVFB @ 25°C 105 95 85 75 65 55 45 35 25 15 5 90 VTTCT Charge Current (mA) 16 16 Figure 3. Oscillator Frequency vs. ROSC Figure 4. VFB & VTTCT Currents vs. ROSC Value 120 100 80 Time, ns 60 40 20 0 Time, ns 0 2 4 6 8 10 Load Capacitance, nF 12 14 16 120 100 80 60 40 20 0 0 2 4 6 8 10 Load Capacitance, nF 12 14 Figure 5. GATE(H) Rise Time vs. Load Capacitance Measured from 4.0 V to 1.0 V with VCC at 5.0 V Figure 6. GATE(H) Fall Time vs. Load Capacitance Measured from 4.0 V to 1.0 V with VCC at 5.0 V 120 100 80 Time, ns 60 40 20 0 Time, ns 0 2 4 6 8 10 Load Capacitance, nF 12 14 16 120 100 80 60 40 20 0 0 2 4 6 8 10 Load Capacitance, nF 12 14 Figure 7. GATE(L) Rise Time vs. Load Capacitance Measured from 1.0 V to 4.0 V with VCC at 5.0 V Figure 8. GATE(L) Fall Time vs. Load Capacitance Measured from 1.0 V to 4.0 V with VCC at 5.0 V http://onsemi.com 10 CS5308 APPLICATIONS INFORMATION Overview The CS5308 DC/DC controller from ON Semiconductor was developed using the Enhanced V2 topology to meet requirements of low voltage, high current loads with fast transient requirements. Enhanced V2 combines the original V2 topology with peak current−mode control for fast transient response and current sensing capability. The addition of an internal PWM ramp and implementation of fast−feedback directly from VCORE has improved transient response and simplified design. The CS5308 includes VTT monitoring, VTTPGD, PWRGD, and MOSFET gate drivers to provide a “fully integrated solution” to simplify design, minimize circuit board area, and reduce overall system cost. Two advantages of a multi−phase converter over a single−phase converter are current sharing and increased apparent output frequency. Current sharing allows the designer to use less inductance in each phase than would be required in a single−phase converter. The smaller inductor will produce larger ripple currents but the total per phase power dissipation is reduced because the RMS current is lower. Transient response is improved because the control loop will measure and adjust the current faster in a smaller output inductor. Increased apparent output frequency is desirable because the off− time and the ripple voltage of the two−phase converter will be less than that of a single−phase converter. Fixed Frequency Multi−Phase Control In a multi−phase converter, multiple converters are connected in parallel and are switched on at different times. This reduces output current from the individual converters and increases the apparent ripple frequency. Because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components. The CS5308 controller uses two−phase, fixed frequency, Enhanced V2 architecture to measure and control currents in individual phases. Each phase is delayed 180° from the previous phase. Normally, GATE(H) transitions to a high voltage at the beginning of each oscillator cycle. Inductor current ramps up until the combination of the current sense signal, the internal ramp and the output voltage ripple trip the PWM comparator and bring GATE(H) low. Once GATE(H) goes low, it will remain low until the beginning of the next oscillator cycle. While GATE(H) is high, the Enhanced V2 loop will respond to line and load variations. On the other hand, once GATE(H) is low, the loop can not respond until the beginning of the next PWM cycle. Therefore, constant frequency Enhanced V2 will typically respond to disturbances within the off−time of the converter. The Enhanced V2 architecture measures and adjusts the output current in each phase. An additional input (CSn) for inductor current information has been added to the V2™ loop for each phase as shown in Figure 9. The triangular inductor current is measured differentially across RS, amplified by CSA and summed with the Channel Startup Offset, the Internal Ramp, and the Output Voltage at the non−inverting input of the PWM comparator. The purpose of the Internal Ramp is to compensate for propagation delays in the CS5308. This provides greater design flexibility by allowing smaller external ramps, lower minimum pulse widths, higher frequency operation, and PWM duty cycles above 50% without external slope compensation. As the sum of the inductor current and the internal ramp increase, the voltage on the positive pin of the PWM comparator rises and terminates the PWM cycle. If the inductor starts a cycle with higher current, the PWM cycle will terminate earlier providing negative feedback. The CS5308 provides a CSn input for each phase, but the CSREF and COMP inputs are common to all phases. Current sharing is accomplished by referencing all phases to the same CSREF and COMP pins, so that a phase with a larger current signal will turn off earlier than a phase with a smaller current signal. http://onsemi.com 11 CS5308 n = 1 or 2 SWNODE Ln RLn RSn CSREF VOUT (VCORE) Internal Ramp “Fast−Feedback” Connection VFB DAC Out COMP + CSn + CSA COn −+ Channel Start−Up Offset + PWM COMP To F/F Reset + E.A. + Figure 9. Enhanced V2 Control Employing Resistive Current Sensing and Additional Internal Ramp Enhanced V2 responds to disturbances in VCORE by employing both “slow” and “fast” voltage regulation. The internal error amplifier performs the slow regulation. Depending on the gain and frequency compensation set by the amplifier’s external components, the error amplifier will typically begin to ramp its output to react to changes in the output voltage in 1−2 PWM cycles. Fast voltage feedback is implemented by a direct connection from VCORE to the non−inverting pin of the PWM comparator via the summation with the inductor current, internal ramp, and OFFSET. A rapid increase in load current will produce a negative offset at VCORE and at the output of the summer. This will cause the PWM duty cycle to increase almost instantly. Fast feedback will typically adjust the PWM duty−cycle in one PWM cycle. As shown in Figure 9, a “partial” internal ramp (nominally 125 mV at a 50% duty cycle) is added to the inductor current ramp at the positive terminal of the PWM comparator. This additional ramp compensates for propagation time delays from the current sense amplifier (CSA), the PWM comparator, and the MOSFET gate drivers. As a result, the minimum ON time of the controller is reduced and lower duty cycles may be achieved at higher frequencies. Also, the additional ramp reduces the reliance on the inductor current ramp and allows greater flexibility when choosing the output inductor and the RCSnCCSn (n = 1 or 2) time constant of the feedback components from VCORE to the CSn pin. Including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. When the average output current is zero, the COMP pin will be: VCOMP + VOUT @ 0 A ) Channel_Startup_Offset ) Int_Ramp ) GCSA @ Ext_Ramp 2 Amplifier Gain (nominally 3.5 V/V), and the Channel Startup Offset is typically 0.40 V. The magnitude of the Ext_Ramp can be calculated from: Ext_Ramp + D @ (VIN * VOUT) (RCSn @ CCSn @ fSW) For example, if VOUT at 0 A is set to 1.745 V with AVP and the input voltage is 5.0 V, the duty cycle (D) will be 1.745/5.0 or 35%. Int_Ramp will be 125 mV • 35/50 = 87.5 mV. Realistic values for RCSn, CCSn and fSW are 60 kW, 0.01 mF, and 300 kHz - using these Ext_Ramp will be 6.3 mV. VCOMP + 1.745 V ) 0.40 V ) 87.5 mV ) 3.5 V V @ 6.3 mV 2 + 2.244 Vdc. If the COMP pin is held steady and the inductor current changes, there must also be a change in the output voltage. Or, in a closed loop configuration when the output current changes, the COMP pin must move to keep the same output voltage. The required change in the output voltage or COMP pin depends on the scaling of the current feedback signal and is calculated as: DV + RS @ GCSA @ DIOUT. The single−phase power stage output impedance is: Single Stage Impedance + DVOUT DIOUT + RS @ GCSA The multi−phase power stage output impedance is the single−phase output impedance divided by the number of phases. The output impedance of the power stage determines how the converter will respond during the first few microseconds of a transient before the feedback loop has repositioned the COMP pin. The peak output current can be calculated from: IOUT,PEAK + (VCOMP * VOUT * Offset) (RS @ GCSA) Int_Ramp is the “partial” internal ramp value at the corresponding duty cycle, Ext_Ramp is the peak−to−peak external steady−state ramp at 0 A, GCSA is the Current Sense 12 Figure 10 shows the step response of the COMP pin at a fixed level. Before T1 the converter is in normal steady state http://onsemi.com CS5308 operation. The inductor current provides a portion of the PWM ramp through the Current Sense Amplifier. The PWM cycle ends when the sum of the current ramp, the “partial” internal ramp voltage signal and Offset exceed the level of the COMP pin. At T1 the output current increases and the output voltage sags. The next PWM cycle begins and the cycle continues longer than previously while the current signal increases enough to make up for the lower voltage at the VFB pin and the cycle ends at T2. After T2 the output voltage remains lower than at light load and the average current signal level (CSn output) is raised so that the sum of the current and voltage signal is the same as with the original load. In a closed loop system the COMP pin would move higher to restore the output voltage to the original level. SWNODE VFB (VOUT) Internal Ramp CSA Out w/ Exaggerated Delays COMP−Offset CSA Out + Ramp + CSREF T1 T2 Figure 10. Open Loop Operation SWNODE Ln CCSn RLn VOUT (VCORE) CSREF Internal Ramp “Fast−Feedback” Connection VFB DAC Out COMP + RCSn n = 1 or 2 CSn + CSA COn −+ Channel Start−Up Offset + PWM COMP To F/F Reset + E.A. + Figure 11. Enhanced V2 Control Employing Lossless Inductive Current Sensing and Internal Ramp Inductive Current Sensing For lossless sensing, current can be sensed across the inductor as shown in Figure 11. In the diagram, L is the output inductance and RL is the inherent inductor resistance. To compensate the current sense signal, the values of RCSn and CCSn are chosen so that L/RL = RCSn • CCSn. If this criteria is met, the current sense signal will be the same shape as the inductor current and the voltage signal at CSn will represent the instantaneous value of inductor current. Also, the circuit can be analyzed as if a sense resistor of value RL was used as a sense resistor (RS). When choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. Cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. Copper magnet wire has a temperature coefficient of 0.39% per °C. The increase in winding resistance at higher temperatures should be considered when setting the ILIM threshold. If a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in Figure 9. Current Sharing Accuracy Printed circuit board (PCB) traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is picked off. For accurate current sharing, the current sense inputs should sense the current at relatively the same point for each phase and the connection to the CSREF pin should be made so that no phase is favored. In some cases, especially with inductive sensing, resistance of the PCB can be useful for increasing the current sense resistance. The total current sense resistance used for calculations must include any PCB trace resistance between the CSn input and the CSREF input that carries inductor current. http://onsemi.com 13 CS5308 Current Sense Amplifier (CSA) input mismatch and the value of the current sense component will determine the accuracy of the current sharing between phases. The worst case Current Sense Amplifier input mismatch is ±5.0 mV and will typically be within 3.0 mV. The difference in peak currents between phases will be the CSA input mismatch divided by the current sense resistance. If all current sense components are of equal resistance a 3.0 mV mismatch with a 2.0 mW sense resistance will produce a 1.5 A difference in current between phases. External Ramp Size and Current Sensing The internal ramp allows flexibility of current sense time constant. Typically, the current sense RCSnCCSn time constant (n = 1 or 2) should be equal to or slower than the inductor’s time constant. If RC is chosen to be smaller (faster) than L/RL, the AC or transient portion of the current sensing signal will be scaled larger than the DC portion. This will provide a larger steady state ramp, but circuit performance will be affected and must be evaluated carefully. The current signal will overshoot during transients and settle at the rate determined by RCSn • CCSn. It will eventually settle to the correct DC level, but the error will decay with the time constant of RCSn • CCSn. If this error is excessive it will effect transient response, adaptive positioning and current limit. During a positive current transient, the COMP pin will be required to overshoot in response to the current signal in order to maintain the output voltage. Similarly, the VDRP signal will overshoot which will produce too much transient droop in the output voltage. Single phase overcurrent will trip earlier than it would if compensated correctly and hiccup mode current limit will have a lower threshold for fast rise step loads than for slowly rising output currents. The waveforms in Figure 12 show a simulation of the current sense signal and the actual inductor current during a positive step in load current with values of L = 500 nH, RL = 1.6 mW, RCSn = 20 k and CCSn = 0.01 mF. For ideal current signal compensation the value of RCSn should be 31 kW. Due to the faster than ideal RC time constant there is an overshoot of 50% and the overshoot decays with a 200 ms time constant. With this compensation the ILIM pin threshold must be set more than 50% above the full load current to avoid triggering hiccup mode during a large output load step. Figure 12. Inductive Sensing Waveform During a Load Step with Fast RC Time Constant (50 ms/div) Current Limit Two levels of over−current protection are provided. First, if the voltage on the Current Sense pins (either CS1 or CS2) exceeds CSREF by more than a fixed threshold (Single Pulse Current Limit), the PWM comparator is turned off. This provides fast peak current protection for individual phases. Second, the individual phase currents are summed and low−pass filtered to compare an averaged current signal to a user adjustable voltage on the ILIM pin. If the ILIM voltage is exceeded, the fault latch trips and the Soft Start capacitor is discharged until the COMP pin reaches 0.27 V. Then Soft Start begins. The converter will continue to operate in a low current hiccup mode until the fault condition is corrected. Overvoltage Protection Overvoltage protection (OVP) is provided as a result of the normal operation of the Enhanced V2 control topology with synchronous rectifiers. The control loop responds to an overvoltage condition within 400 ns, causing the top MOSFET to shut OFF and the synchronous (lower) MOSFET to turn ON. This results in a “crowbar” action to clamp the output voltage and prevent damage to the load. The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. Transient Response and Adaptive Positioning For applications with fast transient currents the output filter is frequently sized larger than ripple currents require in order to reduce voltage excursions during load transients. Adaptive voltage positioning can reduce peak−peak output voltage deviations during load transients and allow for a smaller output filter. The output voltage can be set higher than nominal at light loads to reduce output voltage sag when the load current is applied. Similarly, the output voltage can be set lower than nominal during heavy loads to reduce overshoot when the load current is removed. For low http://onsemi.com 14 CS5308 current applications a droop resistor can provide fast accurate adaptive positioning. However, at high currents the loss in a droop resistor becomes excessive. For example; in a 50 A converter a 1 mW resistor to provide a 50 mV change in output voltage between no load and full load would dissipate 2.5 Watts. Lossless adaptive positioning is an alternative to using a droop resistor, but must respond to changes in load current. Figure 13 shows how adaptive positioning works. The waveform labeled normal shows a converter without adaptive positioning. On the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. With fast (ideal) adaptive positioning the peak to peak excursions are cut in half. In the slow adaptive positioning waveform the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. pin and GND for two reasons. First, this capacitor stabilizes the transconductance error amplifier. Values less than a few nF may cause oscillations of the COMP voltage. These oscillations will increase the output voltage jitter. Second, this capacitor sets the Soft Start time when power is applied to the converter or the converter is enabled. The internal error amplifier will source approximately 30 mA during Soft Start and no switching will occur until the COMP voltage exceeds the Channel Startup Offset (nominally 0.4 V). The COMP voltage will ramp up to the value shown previously (repeated here for convenience): VCOMP + VOUT @ 0 A ) Channel_Startup_Offset ) Int_Ramp ) GCSA @ Ext_Ramp 2 Normal Fast Adaptive Positioning Slow Adaptive Positioning Limits Figure 13. Adaptive Positioning The controller can be configured to adjust the output voltage based on the output current of the converter. (Refer to the application diagram in Figure 1.) To set the no−load positioning, a resistor is placed between the output voltage and VFB pin. The VFB bias current will develop a voltage across the resistor to adjust the no−load output voltage. The VFB bias current is dependent on the value of ROSC as shown in the data sheets. During no−load conditions the VDRP pin is at the same voltage as the VFB pin, so none of the VFB bias current flows through the VDRP resistor. When output current increases the VDRP pin increases proportionally and the VDRP pin current offsets the VFB bias current and causes the output voltage to decrease. The response during the first few microseconds of a load transient are controlled primarily by power stage output impedance and the ESR and ESL of the output filter. The transition between fast and slow positioning is controlled by the total ramp size and the error amp compensation. If the current signal is too large or the error amp too slow there will be a long transition to the final voltage after a transient. This will be most apparent with lower capacitance output filters. Error Amp Compensation & Tuning The RC network between the COMP pin and the Soft Start capacitor (RCMP1 and CCMP1) allows the COMP voltage to slew quickly during transient loading of the converter. Without this network the error amplifier would have to drive the large Soft Start/Stability capacitor directly, which would drastically limit the slew rate of the COMP voltage. The RCMP1/CCMP1 network allows the COMP voltage to undergo a step change in voltage of approximately RCMP1 • ICOMP. The capacitor (CAMP) between the COMP pin and the inverting error amplifier input (the VFB pin) and the parallel combination of the resistors RFBK1 and RDRP1 determine the bandwidth of the error amplifier. The gain of the error amplifier crosses 0 dB at a high enough frequency to give a quick transient response, but well below the switching frequency to minimize ripple and noise on the COMP pin. A capacitor in parallel with the VFB resistor (CFBK2) adds a zero to boost phase near the crossover frequency to improve loop stability. Setting−up and tuning the error amplifier is a three step process. First, the no−load and full−load adaptive voltage positioning (AVP) are set using RFBK1 and RDRP1, respectively. Second, the current sense time constant and error amplifier gain are adjusted with RCSn and CAMP while monitoring VOUT during transient loading. Lastly, the peak−to−peak voltage ripple on the COMP pin is examined when the converter is fully loaded to insure low output voltage jitter. The details of this process are covered in the Design Procedure section. Undervoltage Lockout (UVLO) The transconductance error amplifier requires a capacitor (CCMP2 in the Applications Diagram) between the COMP The controller has undervoltage lockout functions connected to two pins. One, intended for the logic and low−side drivers, with approximately a 4.2 V turn−on threshold is connected to the VCC pin. A second, for the high side drivers, with approximately an 8.25 V threshold, is connected to the VCCH pin. The UVLO threshold for the high side drivers varies with the part type. In many applications this function will be disabled or will only check that the applicable supply is on − not that is at a high enough voltage to run the converter. See individual data sheets for more information on UVLO. http://onsemi.com 15 CS5308 Soft Start Enable, and Hiccup Mode A capacitor between the COMP pin and GND controls Soft Start and hiccup mode slopes. A 0.1 mF capacitor with the 30 mA charge current will allow the output to ramp up at 0.3 V/ms or 1.5 V in 5 ms at start−up. When a fault is detected due to an overcurrent condition the converter will enter a low duty cycle hiccup mode. During hiccup mode the converter will not switch from the time a fault is detected until the Soft Start capacitor has discharged below the Soft Start Discharge Threshold and then charged back up above the Channel Start Up Offset. The COMP pin will disable the converter when pulled below 0.27 V The CS5308 includes VTT monitoring, delay timing and an open−collector VTT Power Good (VTTPGD) output. A comparator with a threshold of approximately 1.05 V monitors VTT. At power−up, VTTPGD is held low and is released a short time after VTT crosses the 1.05 V threshold. The time between VTT stabilizing and the release of VTTPGD is set by a capacitor (CVTT) at the open−collector VTTCT pin. The voltage at the VTTCT pin will ramp from its VCE(sat) voltage, approximately 0.25 V, to 1 V before VTTPGD is pulled HIGH. The VTTCT charging current and CVTT set the VTTPGD delay time. The delay time can be calculated using: TD,VTT + (1 V * 0.25 V) @ CVTT VTTCT_Current. VTT Monitoring & VTT Power Good (VTTPGD) The VTTCT charging current is dependent on the selection of the oscillator frequency. See Figure 3 for a representation of oscillator frequency and charging current versus ROSC value. If either VTT or VTTPGD are held LOW, the internal Fault latch will be SET, the controller will stop switching, and VCORE will be zero. Power Good (PWRGD) The open−collector Power Good (PWRGD) pin is driven by a “window−comparator” monitoring VCORE. This comparator will transition HIGH if VCORE is within ±12% of the nominal VID setting. After a 50 ms delay, the comparators output will saturate the open−collector output transistor and the PWRGD pin will be pulled LOW. Layout Guidelines With the fast rise, high output currents of microprocessor applications, parasitic inductance and resistance should be considered when laying out the power, filter and feedback signal sections of the board. Typically, a multi−layer board with at least one ground plane is recommended. If the layout is such that high currents can exist in the ground plane underneath the controller or control circuitry, the ground plane can be slotted to route the currents away from the controller. The slots should typically not be placed between the controller and the output voltage or in the return path of the gate drive. Additional power and ground planes or islands can be added as required for a particular layout. Gate drives experience high di/dt during switching and the inductance of gate drive traces should be minimized. Gate drive traces should be kept as short and wide as practical and should have a return path directly below the gate trace. Output filter components should be placed on wide planes connected directly to the load to minimize resistive drops during heavy loads and inductive drops and ringing during transients. If required, the planes for the output voltage and return can be interleaved to minimize inductance between the filter and load. The current sense signals are typically tens of milli−volts. Noise pick−up should be avoided wherever possible. Current feedback traces should be routed away from noisy areas such as the switch node and gate drive signals. If the current signals are taken from a location other than directly at the inductor any additional resistance between the pick−off point and the inductor appears as part of the inherent inductor resistances and should be considered in design calculations. The capacitors for the current feedback networks should be placed as close to the current sense pins as practical. After placing the CS5308 control IC, follow these guidelines to optimize the layout and routing: 1. Place the 1 mF power−supply bypass (ceramic) capacitors close to their associated pins: VCCL, VCCH1, VCCH2, VCCL12. 2. Place the MOSFETs to minimize the length of the Gate traces. Orient the MOSFETs such that the Drain connections are away from the controller and the Gate connections are closest to the controller. 3. Place the components associated with the internal error amplifier (RFBK1, CFBK2, CAMP, RCMP1, CCMP1, CCMP2, RDRP1) to minimize the trace lengths to the pins VFB, VDRP and COMP. 4. Place the current sense components (RCS1, RCS2, CCS1, CCS2, RCSREF, CCSREF) near the CS1, CS2, and CSREF pins. 5. Place the frequency setting resistor (ROSC) close to the ROSC pin. The ROSC pin is very sensitive to noise. Route noisy traces, such as the SWNODEs and GATE traces, away from the ROSC pin and resistor. 6. Place the VTT timing capacitor (CVTT) and pull−up resistor (RVTT) near the VTTCT and VTTPGD pins. 7. Place the MOSFETs and output inductors to reduce the size of the noisy SWNODEs. There is a trade−off between reducing the size of the SWNODEs for noise reduction and providing adequate heat−sinking for the synchronous MOSFETs. 8. Place the input inductor and input capacitor(s) near the Drain of the control (upper) MOSFETs. There is a trade−off between reducing the size of this node to save board area and providing adequate heat−sinking for the control MOSFETs. http://onsemi.com 16 CS5308 9. Place the output capacitors (electrolytic and ceramic) close to the processor socket or output connector. 10. The trace from the SWNODEs to the current sense components will be very noisy. Route this away from more sensitive, low−level traces. The Ground layer can be used to help isolate this trace. 11. The Gate traces are very noisy. Route these away from more sensitive, low−level traces. Keep each Gate signal on one layer and insure that there is an uninterrupted return path directly below the Gate trace. The Ground layer can be used to help isolate these traces. 12. Don’t “daisy chain” connections to Ground from one via. Allow each connection to Ground to have its own via as close to the component as possible. 13. Use a slot in the ground plane from the bulk output capacitors back to the input power connector to prevent high currents from flowing beneath the control IC. This slot should extend length−wise under the control IC and separate the connections to “signal ground” and “power ground.” Examples of signal ground include the capacitors at COMP, CSREF, REF, and VTTCT, the resistors at ROSC and ILIM, and the LGND pin to the controller. Examples of power ground include the capacitors to VCCH1, VCCH2 and VCCL12, the Source of the synchronous MOSFETs, and the PGND pin to the controller. 14. The CSREF sense point should be equidistant between the output inductors to equalize the PCB resistance added to the current sense paths. This will insure acceptable current sharing. Also, route the CSREF connection away from noisy traces such as the SWNODEs and GATE traces. If noise from the SWNODEs or GATE signals capacitively couples to the CSREF trace the external ramps will be very noise and voltage jitter will result. 15. Ideally, the SWNODEs are exactly the same shape and the current sense points (connections to RCS1 and RCS2) are made at identical locations to equalize the PCB resistance added to the current sense paths. This will help to insure acceptable current sharing. 16. Place the 0.1 mF ceramic capacitors, CQ1 and CQ2, close to the drains of the MOSFETs Q1 and Q2, respectively. Design Procedure 1. Output Capacitor Selection ripple and bypass the bulk capacitance when the output current changes very quickly. The microprocessor manufacturers usually specify a minimum number of ceramic capacitors. The designer must determine the number of bulk capacitors. Choose the number of bulk output capacitors to meet the peak transient requirements. The formula below can be used to provide a starting point for the minimum number of bulk capacitors (NOUT,MIN): DI NOUT,MIN + ESR per capacitor @ O,MAX DVO,MAX (1) In reality, both the ESR and ESL of the bulk capacitors determine the voltage change during a load transient according to: DVO,MAX + (DIO,MAX Dt) @ ESL ) DIO,MAX @ ESR (2) Unfortunately, capacitor manufacturers do not specify the ESL of their components and the inductance added by the PCB traces is highly dependent on the layout and routing. Therefore, it is necessary to start a design with slightly more than the minimum number of bulk capacitors and perform transient testing or careful modeling/simulation to determine the final number of bulk capacitors. 2. Output Inductor Selection The output capacitors filter the current from the output inductor and provide a low impedance for transient load current changes. Typically, microprocessor applications will require both bulk (electrolytic, tantalum) and low impedance, high frequency (ceramic) types of capacitors. The bulk capacitors provide “hold up” during transient loading. The low impedance capacitors reduce steady−state The output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady−state and transient performance of the converter. When selecting an inductor the designer must consider factors such as DC current, peak current, output voltage ripple, core material, magnetic saturation, temperature, physical size, and cost (usually the primary concern). In general, the output inductance value should be as low and physically small as possible to provide the best transient response and minimum cost. If a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. On the other hand, too low an inductance value will result in very large ripple currents in the power components (MOSFETs, capacitors, etc.) resulting in increased dissipation and lower converter efficiency. Also, increased ripple currents will force the designer to use higher rated MOSFETs, oversize the thermal solution, and use more, higher rated input and output capacitors − the converter cost will be adversely effected. One method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. Lower ripple currents will result in less core and MOSFET losses and higher converter efficiency. Equation 3 may be used to calculate the minimum inductor value to produce a given maximum ripple current (a) per phase. The inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. Conversely, http://onsemi.com 17 CS5308 higher inductor values will result in less than the maximum ripple current. (VIN * VOUT) @ VOUT LoMIN + (a @ IO,MAX @ VIN @ fSW) (3) case input voltage with adequate margin. To calculate the number of input capacitors one must first determine the total RMS input ripple current. To this end, begin by calculating the average input current to the converter: IIN,AVG + IO,MAX @ D h (5) a is the ripple current as a percentage of the maximum output current per phase (a = 0.15 for ±15%, a = 0.25 for ±25%, etc.). If the minimum inductor value is used, the inductor current will swing ± a% about its value at the center (1/2 the DC output current for a two−phase converter). Therefore, for a two−phase converter, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + a) • IO,MAX/2. The maximum inductor value is limited by the transient response of the converter. If the converter is to have a fast transient response then the inductor should be made as small as possible. If the inductor is too large its current will change too slowly, the output voltage will droop excessively, more bulk capacitors will be required, and the converter cost will be increased. For a given inductor value, its interesting to determine the times required to increase or decrease the current. For increasing current: DtINC + Lo @ DIO (VIN * VOUT) (3.1) where: D is the duty cycle of the converter, D = VOUT/VIN; h is the specified minimum efficiency; IO,MAX is the maximum converter output current. The input capacitors will discharge when the control FET is ON and charge when the control FET is OFF as shown in Figure 14. IC,MAX IC,MIN 0A DIC,IN = IC,MAX − IC,MIN tON FET Off, Caps Charging T/2 −IIN,AVG FET On, Caps Discharging For decreasing current: DtDEC + Lo @ DIO (VOUT) (3.2) Figure 14. Input Capacitor Current for a Two−Phase Converter For typical processor applications with output voltages less than half the input voltage, the current will be increased much more quickly than it can be decreased. It may be more difficult for the converter to stay within the regulation limits when the load is removed than when it is applied − excessive overshoot may result. The output voltage ripple can be calculated using the output inductor value derived in this Section (LoMIN), the number of output capacitors (NOUT,MIN) and the per capacitor ESR determined in the previous Section: VOUT,P−P + (ESR per cap NOUT,MIN) @ (VIN * #Phases @ VOUT) @ D (LoMIN @ fSW) (4) The following equations will determine the maximum and minimum currents delivered by the input capacitors: IC,MAX + ILo,MAX h * IIN,AVG IC,MIN + ILo,MIN h * IIN,AVG (6) (7) ILo,MAX is the maximum output inductor current: ILo,MAX + IO,MAX 2 ) DILo 2 (8) ILo,MIN is the minimum output inductor current: ILo,MIN + IO,MAX 2 * DILo 2 (9) This formula assumes steady−state conditions with no more than one phase on at any time. The second term in Equation 4 is the total ripple current seen by the output capacitors. The total output ripple current is the “time summation” of the two individual phase currents that are 180 degrees out−of−phase. As the inductor current in one phase ramps upward, current in the other phase ramps downward and provides a canceling of currents during part of the switching cycle. Therefore, the total output ripple current and voltage are reduced in a multi−phase converter. 3. Input Capacitor Selection DILo is the peak−to−peak ripple current in the output inductor of value Lo: DILo + (VIN * VOUT) @ D (Lo @ fSW) (10) For the two−phase converter, the input capacitor(s) RMS current is then: ICIN,RMS + [2D @ (IC,MIN2 ) IC,MIN @ DIC,IN (11) ) DIC,IN2 3) ) IIN,AVG2 @ (1 * 2D)]1 2 Select the number of input capacitors (NIN) to provide the RMS input current (ICIN,RMS) based on the RMS ripple current rating per capacitor (IRMS,RATED): NIN + ICIN,RMS IRMS,RATED (12) The choice and number of input capacitors is primarily determined by their voltage and ripple current ratings. The designer must choose capacitors that will support the worst http://onsemi.com 18 CS5308 For a two−phase converter with perfect efficiency (h = 1), the worst case input ripple−current will occur when the converter is operating at a 25% duty cycle. At this operating point, the parallel combination of input capacitors must support an RMS ripple current equal to 25% of the converter’s DC output current. At other duty cycles, the ripple−current will be less. For example, at a duty cycle of either 10% or 40%, the two−phase input ripple−current will be approximately 20% of the converter’s DC output current. In general, capacitor manufacturers require derating to the specified ripple−current based on the ambient temperature. More capacitors will be required because of the current derating. The designer should be cognizant of the ESR of the input capacitors. The input capacitor power loss can be calculated from: PCIN + ICIN,RMS2 @ ESR_per_capacitor NIN (13) MAX dI/dt occurs in first few PWM cycles. ILi Li TBD Ci 2 × 6SP680 + Vi − 5.0 V ESRCi 13 m/2 = 6.5 m Vi(t = 0) = 5.0 V Q1 SWNODE ILo Lo 825 nH + Co Low ESR capacitors are recommended to minimize losses and reduce capacitor heating. The life of an electrolytic capacitor is reduced 50% for every 10°C rise in the capacitor’s temperature. 4. Input Inductor Selection The use of an inductor between the input capacitors and the power source will accomplish two objectives. First, it will isolate the voltage source and the system from the noise generated in the switching supply. Second, it will limit the inrush current into the input capacitors at power up. Large inrush currents will reduce the expected life of the input capacitors. The inductor’s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. VOUT Vo(t = 0) = 1.745 V + VCi 5 × 6.3ZA1000M10x16 Q2 ESRCo 23 m/5 = 4.6 m 14 u(t) Figure 15. Calculating the Input Inductance The worst case input current slew rate will occur during the first few PWM cycles immediately after a step−load change is applied as shown in Figure 15. When the load is applied, the output voltage is pulled down very quickly. Current through the output inductors will not change instantaneously so the initial transient load current must be conducted by the output capacitors. The output voltage will step downward depending on the magnitude of the output current (IO,MAX), the per capacitor ESR of the output capacitors (ESROUT), and the number of the output capacitors (NOUT) as shown in Figure . Assuming the load current is shared equally between the two phases, the output voltage at full, transient load will be: VOUT,FULL−LOAD + (14) the output inductor (the SWNODE). At that instant, the voltage across the output inductor can be calculated as: DVLo + VIN * VOUT,FULL−LOAD + VIN * VOUT,NO−LOAD ) (IO,MAX 2) @ ESROUT NOUT (15) The differential voltage across the output inductor will cause its current to increase linearly with time. The slew rate of this current can be calculated from: dILo dt + DVLo Lo (16) VOUT,NO−LOAD * (IO,MAX 2) @ ESROUT NOUT When the control MOSFET (Q1 in Figure 15) turns ON, the input voltage will be applied to the opposite terminal of Current changes slowly in the input inductor so the input capacitors must initially deliver the vast majority of the input current. The amount of voltage drop across the input capacitors (DVCi) is determined by the number of input capacitors (NIN), their per capacitor ESR (ESRIN), and the current in the output inductor according to: http://onsemi.com 19 CS5308 DVCi + ESRIN NIN @ dILo dt @ tON + ESRIN NIN @ dILo dt @ D fSW (17) Before the load is applied, the voltage across the input inductor (VLi) is very small − the input capacitors charge to the input voltage, VIN. After the load is applied the voltage drop across the input capacitors, DVCi, appears across the input inductor as well. Knowing this, the minimum value of the input inductor can be calculated from: LiMIN + VLi + DVCi dIIN dtMAX dIIN dtMAX (18) switching losses. The third term is the losses associated with the control and synchronous MOSFET output charge when the control MOSFET turns ON. The output losses are caused by both the control and synchronous MOSFET but are dissipated only in the control FET. The fourth term is the loss due to the reverse recovery time of the body diode in the synchronous MOSFET. The first two terms are usually adequate to predict the majority of the losses. Where IRMS,CNTL is the RMS value of the trapezoidal current in the control MOSFET: IRMS,CNTL + D (20) dIIN/dtMAX is the maximum allowable input current slew rate (specified as 0.1 A/ms or 0.1 × 106 A/s for VRM 8.5). The input inductance value calculated from Equation 18 is relatively conservative. It assumes the supply voltage is very “stiff” and does not account for any parasitic elements that will limit dI/dt such as stray inductance. Also, the ESR values of the capacitors specified by the manufacturer’s data sheets are worst case high limits. In reality input voltage “sag,” lower capacitor ESRs, and stray inductance will help reduce the slew rate of the input current. As with the output inductor, the input inductor must support the maximum current without saturating the magnetic. Also, for an inexpensive iron powder core, such as the −26 or −52 from Micrometals, the inductance “swing” with DC bias must be taken into account − inductance will decrease as the DC input current increases. At the maximum input current, the inductance must not decrease below the minimum value or the dI/dt will be higher than expected. 5. MOSFET & Heatsink Selection @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2 ILo,MAX is the maximum output inductor current: ILo,MAX + IO,MAX 2 ) DILo 2 (21) ILo,MIN is the minimum output inductor current: ILo,MIN + IO,MAX 2 * DILo 2 (22) IO,MAX is the maximum converter output current. D is the duty cycle of the converter: D + VOUT VIN (23) DILo is the peak−to−peak ripple current in the output inductor of value Lo: DILo + (VIN * VOUT) @ D (Lo @ fSW) (24) Power dissipation, package size, and thermal solution drive MOSFET selection. To adequately size the heat sink, the design must first predict the MOSFET power dissipation. Once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The control or upper MOSFET will display both switching and conduction losses. The synchronous or lower MOSFET will exhibit only conduction losses because it switches into nearly zero voltage. However, the body diode in the synchronous MOSFET will suffer diode losses during the non−overlap time of the gate drivers. For the upper or control MOSFET, the power dissipation can be approximated from: PD,CONTROL + (IRMS,CNTL2 @ RDS(on)) ) (ILo,MAX @ Qswitch Ig @ VIN @ fSW) ) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW) (19) RDS(on) is the ON resistance of the MOSFET at the applied gate drive voltage. Qswitch is the post gate threshold portion of the gate−to−source charge plus the gate−to−drain charge. This may be specified in the data sheet or approximated from the gate−charge curve as shown in the Figure 16. Qswitch + Qgs2 ) Qgd (25) ID VGATE VGS_TH QGS1 QGS2 QGD VDRAIN Figure 16. MOSFET Switching Characteristics The first term represents the conduction or IR losses when the MOSFET is ON while the second term represents the Ig is the output current from the gate driver IC. VIN is the input voltage to the converter. fsw is the switching frequency of the converter. http://onsemi.com 20 CS5308 QG is the MOSFET total gate charge to obtain RDS(on). Commonly specified in the data sheet. Vg is the gate drive voltage. QRR is the reverse recovery charge of the lower MOSFET. Qoss is the MOSFET output charge specified in the data sheet. For the lower or synchronous MOSFET, the power dissipation can be approximated from: PD,SYNCH + (IRMS,SYNCH2 @ RDS(on)) ) (Vfdiode @ IO,MAX 2 @ t_nonoverlap @ fSW) (26) All terms were defined in the previous discussion for the control MOSFET with the exception of: IRMS,SYNCH + 1 * D (27) @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2 The first term represents the conduction or IR losses when the MOSFET is ON and the second term represents the diode losses that occur during the gate non−overlap time. RCS1 L1 0A CS1 where: Vfdiode is the forward voltage of the MOSFET’s intrinsic diode at the converter output current. t_nonoverlap is the non−overlap time between the upper and lower gate drivers to prevent cross conduction. This time is usually specified in the data sheet for the control IC. +− − + + w − GVDRP COMP VID Setting IBIAS VFB RVFBK VFB = VID VCORE CCS1 Error Amp RDRP RCS2 L2 0A CS2 CCS2 CSREF + − GVDRP VDRP = VID IDRP = 0 IFBK = IBIASVFB VCORE = VID + IBIASVFB w RVFBk Figure 17. AVP Circuitry at No−Load When the MOSFET power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature qT t (TJ * TA) PD (28) Pad Size (in2/mm2) 0.50/323 0.75/484 1.00/645 1.50/968 Single−Sided 1 oz. Copper 60−65°C/W 55−60°C/W 50−55°C/W 45−50°C/W where: qT is the total thermal impedance (qJC + qSA); qJC is the junction−to−case thermal impedance of the MOSFET; qSA is the sink−to−ambient thermal impedance of the heatsink assuming direct mounting of the MOSFET (no thermal “pad” is used); TJ is the specified maximum allowed junction temperature; TA is the worst case ambient operating temperature. For TO−220 and TO−263 packages, standard FR−4 copper clad circuit boards will have approximate thermal resistances (qSA) as shown below: As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e., worst case MOSFET RDS(on)). Also, the inductors and capacitors share the MOSFET’s heatsinks and will add heat and raise the temperature of the circuit board and MOSFET. For any new design, its advisable to have as http://onsemi.com 21 CS5308 much heatsink area as possible − all too often new designs are found to be too hot and require re−design to add heatsinking. 6. Adaptive Voltage Positioning There are two resistors that determine the Adaptive Voltage Positioning: RVFBK and RDRP. RVFBK establishes the no−load “high” voltage position and RDRP determines the full−load “droop” voltage. Resistor RVFBK is connected between VCORE and the VFB pin of the controller. At no load, this resistor will conduct the internal bias current of the VFB pin and develop a voltage drop from VCORE to the VFB pin. Because the error amplifier regulates VFB to the DAC setting, the output voltage, VCORE, will be higher by the amount IBIASVFB • RVFBK. This condition is shown in Figure 17. To calculate RVFBK the designer must specify the no−load voltage increase above the VID setting (DVNO−LOAD) and determine the VFB bias current. Usually, the no−load voltage RCS1 L1 IMAX/2 CS1 increase is specified in the design guide for the processor that is available from the manufacturer. The VFB bias current is determined by the value of the resistor from ROSC to ground (see Figure in the data sheet for a graph of IBIASVFB versus R_OSC). The value of RVFBK can then be calculated: RVFBK + DVNO−LOAD IBIASVFB (29) Resistor RDRP is connected between the VDRP and the VFB pins. At no−load, the VDRP and the VFB pins will both be at the DAC voltage so this resistor will conduct zero current. However, at full−load, the voltage at the VDRP pin will increase proportional to the output inductor’s current while VFB will still be regulated to the DAC voltage. Current will be conducted from VDRP to VFB by RDRP. This current will be large enough to supply the VFB bias current and cause a voltage drop from VFB to VCORE across RFBK − the converter’s output voltage will be reduced. This condition is shown in Figure 18. +− − + + w − GVDRP COMP VID Setting IBIAS VFB RVFBK VCORE CCS1 Error Amp RDRP RCS2 L2 IMAX/2 CS2 + − GVDRP VDRP = VID + VFB = VID IMAX • RL • GVDRP IDRP IFBK CCS2 CSREF IDRP = IMAX • RL • GVDRP/RDRP IFBK = IDRP − IBIASVFB VCORE = VID − (IDRP − IBIASVFB) w RVFBK = VID − IMAX w RL w GVDRP w RFBK/RDRP + IBIASVFB w RFBK Figure 18. AVP Circuitry at Full−Load To determine the value of RDRP the designer must specify the full−load voltage reduction from the VID (DAC) setting (DVOUT,FULL−LOAD) and predict the voltage increase at the VDRP pin at full−load. Usually, the full−load voltage reduction is specified in the design guide for the processor that is available from the manufacturer. To predict the voltage increase at the VDRP pin at full−load (DVDRP), the designer must consider the output inductor’s resistance (RL), the PCB trace resistance between the current sense points (RPCB), and the controller IC’s gain from the current sense to the VDRP pin (GVDRP): DVDRP + IO,MAX @ (RL ) RPCB) @ GVDRP (30) DVOUT,FULL−LOAD is the full−load voltage reduction from the VID (DAC) setting. DVOUT,FULL−LOAD is not the voltage change from the no−load AVP setting. 7. Current Sensing For inductive current sensing, choose the current sense network (RCSn, CCSn, n = 1 or 2) to satisfy RCSn @ CCSn + Lo (RL ) RPCB) (32) For resistive current sensing, choose the current sense network (RCSn, CCSn, n = 1 or 2) to satisfy RCSn @ CCSn + Lo (Rsense) (33) The value of RDRP can then be calculated: DVDRP RDRP + (IBIASVFB ) DVOUT,FULL−LOAD RVFBK) (31) This will provide an adequate starting point for RCSn and CCSn. After the converter is constructed, the value of RCSn (and/or CCSn) should be fine−tuned in the lab by observing the VDRP signal during a step change in load current. Tune http://onsemi.com 22 CS5308 the RCSn • CCSn network to provide a “square−wave” at the VDRP output pin with maximum rise time and minimal overshoot as shown in Figure 21. Figure 19. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Too Long (Slow): VDRP and VOUT Respond Too Slowly. Figure 21. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Optimal: VDRP and VOUT Respond to the Load Current Quickly Without Overshooting. 8. Error Amplifier Tuning After the steady−state (static) AVP has been set and the current sense network has been optimized the Error Amplifier must be tuned. Basically, the gain of the Error Amplifier should be adjusted to provide an acceptable transient response by increasing or decreasing the Error Amplifier’s feedback capacitor (CAMP in the Applications Diagram). The bandwidth of the control loop will vary directly with the gain of the error amplifier. Figure 20. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Too Short (Fast): VDRP and VOUT Both Overshoot. Figure 22. The Value of CAMP Is Too High and the Loop Gain/Bandwidth Too Low. COMP Slews Too Slowly Which Results in Overshoot in VOUT. If CAMP is too large the loop gain/bandwidth will be low, the COMP pin will slew too slowly, and the output voltage will overshoot as shown in Figure 22. On the other hand, if http://onsemi.com 23 CS5308 CAMP is too small the loop gain/bandwidth will be high, the COMP pin will slew very quickly and overshoot. Integrator “wind up” is the cause of the overshoot. In this case the output voltage will transition more slowly because COMP spikes upward as shown in Figure 23. Too much loop gain/bandwidth increase the risk of instability. In general, one should use the lowest loop gain/bandwidth as possible to achieve acceptable transient response − this will insure good stability. If CAMP is optimal the COMP pin will slew quickly but not overshoot and the output voltage will monotonically settle as shown in Figure 24. ripple on the COMP pin will contribute to output voltage jitter. Figure 25. At Full−Load (28 A) the Peak−to−Peak Voltage Ripple on the COMP Pin Should Be Less than 20 mV for a Well−Tuned/Stable Controller. Higher COMP Voltage Ripple Will Contribute to Output Voltage Jitter. 9. Current Limit Setting Figure 23. The Value of CAMP Is Too Low and the Loop Gain/Bandwidth Too High. COMP Moves Too Quickly, Which Is Evident from the Small Spike in Its Voltage When the Load Is Applied or Removed. The Output Voltage Transitions More Slowly Because of the COMP Spike. When the output of the current sense amplifier (CO1 or CO2 in the block diagram) exceeds the voltage on the ILIM pin the part will enter hiccup mode. For inductive sensing, the ILIM pin voltage should be set based on the inductor’s maximum resistance (RLMAX). The design must consider the inductor’s resistance increase due to current heating and ambient temperature rise. Also, depending on the current sense points, the circuit board may add additional resistance. In general, the temperature coefficient of copper is +0.39% per °C. If using a current sense resistor (RSENSE), the ILIM pin voltage should be set based on the maximum value of the sense resistor. To set the level of the ILIM pin: VILIM + (IOUT,LIM ) DILo 2) @ R @ GILIM (34) Figure 24. The Value of CAMP Is Optimal. COMP Slews Quickly Without Spiking or Ringing. VOUT Does Not Overshoot and Monotonically Settles to Its Final Value. where: IOUT,LIM is the current limit threshold of the converter; DILo/2 is half the inductor ripple current; R is either (RLMAX + RPCB) or RSENSE; GILIM is the current sense to ILIM gain. For the overcurrent protection to work properly, the current sense time constant (RC) should be slightly larger than the RL time constant. If the RC time constant is too fast, during step load changes the sensed current waveform will appear larger than the actual inductor current and will probably trip the current limit at a lower level than expected. 10. PWM Comparator Input Voltage After the control loop is tuned to provide an acceptable transient response the steady−state voltage ripple on the COMP pin should be examined. When the converter is operating at full, steady−state load, the peak−to−peak voltage ripple on the COMP pin should be less than 20 mVPP as shown in Figure 25. Less than 10 mVPP is ideal. Excessive The voltage at the positive input terminal of the PWM comparator (see Figure 9 or 11) is limited by the internal voltage supply of the controller (3.3 V), the size of the internal ramp, and the magnitude of the channel startup offset voltage. To prevent the PWM comparator from http://onsemi.com 24 CS5308 saturating, the differential input voltage from CSREF to CSn (n = 1 or 2) must satisfy the following equation: VCSREF,MAX ) VCOn,MAX ) 310 mV @ D v 2.45 V (35) where: VCSREF,MAX + Max VID Setting w AVP @ Full Load VCOn,MAX + [VCSn * VCSREF] @ GCSA,MAX + (IO,MAX 2 ) DILo 2) @ RMAX @ GCSA,MAX RMAX + RSENSE or (RL,MAX ) RPCB,MAX) 11. VTTPGD Delay Time Setting value from the VTTCT pin to ground (CVTT) determine the TD,VTT delay time. However, the choice of oscillator frequency and the value of ROSC set the VTTCT charge current as shown in Figure 4. Therefore, delay time is simply set by the value of CVTT according to the following equation: TD,VTT + (1 V * 0.25V) @ CVTT VTTCT_Current 12. Soft Start Time (36) The Soft Start time (TSS) can be calculated from: TSS + (VCOMP * RCMP1 @ ICOMP) @ CCMP2 ICOMP (37) where: VCOMP + VOUT @ 0 A ) Channel_Startup_Offset ) Int_Ramp ) GCSA @ Ext_Ramp 2 The VTTPGD signal is pulled LOW a predetermined delay time (TD,VTT) after the VTT voltage crosses the VTT Threshold. The VTTCT charge current and the capacitor ICOMP is the COMP source current from the data sheet. http://onsemi.com 25 CS5308 Design Example Typical Design Requirements: VOUT,P−P + (ESR per cap NOUT,MIN) @ (VIN * #Phases @ VOUT) @ D (LoMIN @ fSW) (4) VIN = 5.0 Vdc VOUT = 1.70 Vdc (nominal) VOUT,RIPPLE = 10 mVPP max VID Range: 1.050 Vdc − 1.825 Vdc IO,MAX = 28 A at full−load IOUT,LIM = 33 A min at 50°C (shutdown threshold) dIIN/dt = 0.1 A/ms max fSW = 335 kHz h = 81% minimum TA,MAX = 60°C TJ,MAX = 115°C TD,VTT = 2.5 ms (VTTPGD delay time) TSS = 6.5 ms (Soft Start time) DVOUT at no−load (static) = +45 mV from VID setting = 1.745 Vdc DVOUT at full−load (static) = −45 mV from VID setting = 1.655 Vdc DVOUT at full−load (transient) = -90 mV from VID setting = 1.610 Vdc 1. Output Capacitor Selection + (24 mW 5) @ (5.0 V * 2 @ 1.7 V) @ (1.7 V 5.0 V) (825 nH @ 335 kHz) + (4.8 mW) @ {1.97 A} + 9.45 mV The output voltage ripple will be decreased when output capacitors are added to satisfy transient loading requirements. We will need the nominal and worst case inductor resistances for subsequent calculations: RL + 5 turns @ 3.19 cm turn @ 0.03218 ft cm @ 2 mW ft + 1.03 mW The inductor resistance will be maximized when the inductor is “hot” due to the load current and the ambient temperature is high. Assuming a 40°C temperature rise of the inductor at full−load and a 25°C ambient temperature rise we can calculate: RL,MAX + 1.03 mW @ [1 ) 0.39% °C @ (40°C ) 25°C)] + 1.29 mW 3. Input Capacitor Selection First, choose a low−cost, low−ESR output capacitor such as the Rubycon 6.3ZA1000M10X16: 6.3 V, 1000 mF, 1.65 ARMS, 24 mW, 10 × 16 mm. Calculate the minimum number of output capacitors: NOUT,MIN + ESR per capacitor @ DIO,MAX DVO,MAX (1) Use Equation 5 to determine the average input current to the converter: IIN,AVG + IO,MAX @ D h + 28 A @ (1.655 V 5.0 V) 0.81 + 11.44 A (5) + 24 mW @ 28 A (1.745 V * 1.610 V) + 4.987 or 5 capacitors minimum (5000 mF) 2. Output Inductor Selection Next, use Equations 6 to 10: DILo + (VIN * VOUT) @ D (Lo @ fSW) + (5 V * 1.655 V) @ + 4.00 App ILo,MAX + IO,MAX 2 ) DILo 2 + 28 A 2 ) 4 App 2 + 16 A ILo,MIN + IO,MAX 2 * DILo 2 + 28 A 2 * 4 App 2 + 12 A IC,MAX + ILo,MAX h * IIN,AVG + 16 A 0.81 * 11.44 A + 8.3 A IC,MIN + ILo,MIN h * IIN,AVG + 12 A 0.81 * 11.44 A + 3.3 A (7) (8) (10) Calculate the minimum output inductance at IO,MAX according to Equation 3 with ±20% inductor ripple current (a = 0.20): (VIN * VOUT) @ VOUT LoMIN + (a @ IO,MAX @ VIN @ fSW) + (5 V * 1.655 V) @ 1.655 V (0.2 @ 28 A @ 5 V @ 335 kHz) (3) (1.655 V 5.0 V) (825 nH @ 335 kHz) + 590 nH To save cost, we choose the inexpensive T50-52 core from Micrometals: 33 nH/N2, 3.19 cm./turn. At 14 A per phase the permeability of this core will be approximately 80% of the permeability at 0 A. Therefore, at 0 A we must achieve at least 590 nH/0.8 or 738 nH. Using four turns results in only 528 nH, so we must use five turns of #16AWG bifilar (2 mW/ft.) to produce 825 nH. This inductor is available as part number CTX22−15401 from Coiltronics. Use Equation 4 to insure the output voltage ripple will satisfy the design goal with the minimum number of capacitors and the nominal output inductance: (9) (6) For the two−phase converter, the input capacitor(s) RMS current is then (Note: D = 1.655 V/5 V = 0.331): http://onsemi.com 26 CS5308 ICIN,RMS + [2D @ (IC,MIN2 ) IC,MIN @ DIC,IN (11) ) DIC,IN2 3) ) IIN,AVG2 @ (1 * 2D)]1 2 + [0.662 @ (3.32 ) 3.3 @ 5 ) 52 3) ) 11.442 @ (1 * 0.662)]1 2 + 8.94 ARMS 2.89 or 3 turns to achieve the minimum inductance value. With three turns the input inductor will be: Li + 32 @ 33.5 nH N2 + 301 nH This inductor is available as part number CTX15−14771 from Coiltronics. At this point, the designer must decide between saving board space by using higher−rated/more costly capacitors or saving cost by using more lower−rated/less costly capacitors. To save board space, we choose the SP (Oscon) series capacitors by Sanyo: 680 mF, 6.3 V, 4.84 ARMS, 13 mW, 10 × 10.5mm. We need approximately 8.94 A/4.84 A = 1.84 or NIN = 2 capacitors on the input for a conservative design. 4. Input Inductor Selection The input inductor must limit the input current slew rate to less than 0.1 A/ms during a load transient from 0 to 28 A. A conservative value will be calculated assuming the minimum number of output capacitors (NOUT = 5), two input capacitors (NIN = 2), worst case ESR values for both the input and output capacitors, and a maximum duty cycle (D = (1.825 V + 45 mVAVP)/5.0 VIN = 0.374). First, use Equation 15 to calculate the voltage across the output inductor due to the 28 A load current being shared equally between the two phases: DVLo + VIN * VOUT,NO−LOAD ) (IO,MAX 2) @ ESROUT NOUT + 5.0 V * 1.87 V ) 14 A @ 23 mW 5 + 3.194 V (15) Figure 26. CS5308 Circuitry With Only 5 Rubycon Output Capacitors, 2 Oscon Input Capacitors and a 300 nH Input Inductor. The dIIN/dt of the Input Current (0.064 A/ms) Is Much Lower Than Expected (0.1 A/ms) Because of Input Voltage Drop and Lower Real ESRs Than Specified in the Capacitors’ Data Sheets. 5. MOSFET & Heatsink Selection Second, use Equation 16 to determine the rate of current increase in the output inductor: dILo dt + DVLo Lo + 3.194 V 825 nH + 3.872 V ms (16) Finally, use Equations 17 and 18 to calculate the minimum input inductance value: DVCi + ESRIN NIN @ dILo dt @ D fSW + 13 mW 2 @ 3.872 ms @ 0.374 335 kHz + 28.1 mV LiMIN + DVCi dIIN dtMAX (18) (17) + 28.1 mV 0.1 A ms + 281 nH The NTB75N03−06 from ON Semiconductor is chosen for both the control and synchronous MOSFET due to its low RDS(on) and low gate−charge requirements. The following parameters are derived from the NTB75N03−06 data sheet: RDS(on) = 5.3 mW QSWITCH = 29 nC QG = 52 nC QRR = 23 nC QOSS = 35 nC (approx.) Vfdiode = 0.76 V @ 15 A qJC = 1.0°C / W CS5308 Parameters: iG = 1 A VG = 10 V t_nonoverlap = 65 ns The RMS value of the current in the control MOSFET is calculated from Equation 20 and the previously derived values for D, ILMAX, and ILMIN at the converter’s maximum output current: We choose the small, cost effective T30−26 core from Micrometals (33.5 nH/N2) with #16 AWG. We need at least http://onsemi.com 27 CS5308 IRMS,CNTL + D @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN (20) ) ILo,MIN2) 3]1 2 + 0.575 @ [(162 ) 16 @ 12 ) 122) 3]1 2 + 8.08 ARMS 6. Adaptive Voltage Positioning Equation 19 is used to calculate the power dissipation of the control MOSFET: PD,CONTROL + (IRMS,CNTL2 @ RDS(on)) ) (ILo,MAX @ Qswitch Ig @ VIN @ fSW) ) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW) + (8.082 ARMS @ 5.3 mW) ) (16 A @ 29 nC 1 A @ 5 V @ 335 kHz) ) (35 nC 2 @ 5 V @ 335 kHz) ) (5 V @ 23 nC @ 335 kHz) + 0.346 W ) 0.78 W ) 0.03 W ) 0.04 W + 1.2 W (19) First, to achieve the 335 kHz switching frequency, use Figure 3 to determine that a 39 kW resistor is needed for ROSC. Then, use Figure 4 to find the VFB bias current at the corresponding value of ROSC. In this example, the 39 kW ROSC resistor results in a VFB bias current of approximately 7.0 mA. Knowing the VFB bias current, one can calculate the required values for RVFBK and RDRP using Equations 29 through 31. The no−load position is easily set using Equation 29: RVFBK + DVNO−LOAD IBIASVFB + +45 mV 7.0 mA + 6.49 kW (29) The RMS value of the current in the synchronous MOSFET is calculated from Equation 27 and the previously derived values for D, ILo,MAX, and ILo,MIN at the converter’s maximum output current: IRMS,SYNCH + 1 * D + 0.669 @ [(162 ) 16 @ 12 ) 122) 3]1 2 + 11.5 ARMS (27) For inductive current sensing, the designer must calculate the inductor’s resistance (RL) and approximate any resistance added by the circuit board (RPCB). We found the inductor’s nominal resistance in Section 2 (1.03 mW). In this example, we approximate 0.75 mW for the circuit board resistance (RPCB). With this information, Equation 30 can be used to calculate the increase at the VDRP pin at full load; DVDRP + IO,MAX @ (RL ) RPCB) @ GVDRP + 28 A @ (1.03 mW ) 0.75 mW) @ 3.2 V V + 159 mV (30) @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2 RDRP can then be calculated from Equation 31: RDRP + (IBIAS (31) DVDRP ) DVOUT,FULL−LOAD RVFBK) VFB + 159 mV (7.0 mA ) 45 mV 6.49 kW) + 11.5 kW 7. Current Sensing Equation 26 is used to calculate the power dissipation of the synchronous MOSFET: PD,SYNCH + (IRMS,SYNCH2 @ RDS(on)) + (11.52 ARMS @ 5.3 mW) ) (0.76 V @ 28 A 2 @ 65 ns @ 335 kHz) + 0.70 W ) 0.23 W + 0.93 W (26) ) (Vfdiode @ IO,MAX 2 @ t_nonoverlap @ fSW) Choose the current sense network (RCSn, CCSn, n = 1 or 2) to satisfy RCSn @ CCSn + Lo (RL ) RPCB) (30) Equation 28 is used to calculate the heat sink thermal impedances necessary to maintain less than the specified maximum junction temperatures at 60°C ambient: qCNTL t (115 * 60°C) 1.2 W * 1.0°C W + 46°C W qSYNCH t (115 * 60°C) 0.93 W * 1.0°C W + 59°C W The component values determined thus far are Lo = 825 nH, RL = 1.03 mW, and RPCB = 0.75mW. We choose a convenient value for CCS1 (0.01 mF) and solve for RCS1: RCSn + 825 nH (1.03 mW ) 0.75 mW) 0.01 mF + 46 kW or 50 kW when rounded up. If board area permits, a cost effective heatsink could be formed by using a TO−263 mounting pad of at least 1.0− 1.5 in2 per MOSFET on a single−sided, 1 oz. copper PCB (or 0.5 to 0.75 in2 on each side of a two−sided board). If board space must be conserved, AAVID offers clip−on heatsinks for TO−220 thru−hole packages. Examples of these heatsinks include #577002 (1″ × 0.75″ × 0.25″, 39°C/W at 1 W) and #591302 (0.75″ × 0.5″ × 0.5″, 34°C/W at 1 W) After the circuit is constructed, the values of RCSn and/or CCSn should be tuned to provide a “square−wave” at VDRP with minimal overshoot and fast rise time due to a step change in load current as shown in Figures 19−21. Based on experience, the starting value for RCSn is probably too low and will need to be increased to provide a current sense signal similar to those in Figure 21. Equation 30 will be most accurate for higher quality iron powder core materials such as the −2 or −8 from Micrometals. The permeability of these more expensive http://onsemi.com 28 CS5308 cores is relatively constant versus DC current, AC flux density and frequency. Less expensive core materials (such as the −52 from Micrometals) change their characteristics versus DC current, AC flux density, and frequency. The less expensive materials may yield acceptable converter performance if the current sense time constant is set approximately 2× longer than anticipated. For example, use approximately twice the resistance (RCSn) or twice the capacitance (CCSn) when using the less expensive core material. If we use −52 material for this design, the value of RCSn should be increased to 2 × 50 kW or 100 kW. 8. Error Amplifier Tuning 3.3 VREF RLIM1 ?? RLIM2 1k VLIM To ILIM Pin Figure 27. Setting the Current Limit 10. PWM Comparator Input Voltage The error amplifier is tuned by adjusting CAMP to provide an acceptable full−load transient response as shown in Figures 22−24. After a value for CAMP is chosen, the peak−to−peak voltage ripple on the COMP pin is examined under full−load to insure less than 20 mVPP as shown in Figure 25. 9. Current Limit Setting Use Equation 35 to check the voltage level to the positive pin of the internal PWM comparators to insure the design will not saturate the comparator at maximum DAC output voltage with 1% error, AVP at full−load, 100% duty cycle (D = 1), and maximum internal ramp (310 mV at 100% duty−cycle): VCSREF,MAX + Max VID Setting w AVP @ Full−Load + 1.01 @ 1.825 V * 45 mV + 1.80 V VCOn,MAX + (IO,MAX 2 ) DILo 2) @ RMAX @ GCSA,MAX + (28 A 2 ) 4.0 A 2) @ (1.29 mW ) 0.82 mW) @ 3.95 V V + 0.133 V VCSREF,MAX ) VCOn,MAX ) 310 mV @ D + 1.80 V ) 0.133 V ) 310 mV + 2.243 V (35) The maximum inductor resistance, the maximum PCB resistance, and the maximum current−sense gain as shown in Equation 34 determine the current limit. The maximum current, IOUT,LIM, was specified in the design requirements. The maximum inductor resistance occurs at full−load and the highest ambient temperature. This value was found in the “Output Inductor Section” (1.58 mW). The PCB resistance increases due to the change in ambient temperature: RPCB,MAX + 0.75 mW @ (1 ) 0.39% °C @ (60 * 25)°C) + 0.85 mW VILIM + (IOUT,LIM ) DILo 2) @ (RLMAX ) RPCB,MAX) @ GILIM + (33 A ) 4.0 A 2) @ (1.29 mW ) 0.85 mW) @ 6.5 V V + 0.486 Vdc This value is acceptable because it is below the specified maximum of 2.45 V. To obtain the 335 kHz switching frequency the value of ROSC was set to 39 kW in Section 6. Figure 4 must be used to determine the value of the VTTCT Charge Current at this ROSC value. In this example, the 39 kW ROSC resistor results in a VTTCT Charge Current of approximately 26 mA. Using Equation 34 and solving for CVTT: TD,VTT + (1 V * 0.25 V) @ CVTT VTTCT_Current (34) CVTT + TD,VTT @ VTTCT_Current 0.75 V + 2.5 ms @ 26 mA 0.75 V + 0.086 mF or 0.1 mF 11. VTTPGD Delay Time Setting Set the voltage at the ILIM pin using a resistor divider from the 3.3 V reference output as shown in Figure 27. If the resistor from ILIM to GND is chosen as 1 k (RLIM2), the resistor from ILIM to 3.3 V can be calculated from: RLIM1 + (VREF * VILIM) (VILIM RLIM2) + (3.3 V * 0.486 V) (0.486 V 1 kW) + 5790W or 5.76 kW http://onsemi.com 29 CS5308 12. Soft Start Time To set the Soft Start time we first approximate the COMP voltage at a duty−cycle of D = 1.745 V/5 V = 0.349: VCOMP + VOUT @ 0 A ) Channel_Startup_Offset ) Int_Ramp + 1.745 V ) 0.40 V ) 250 mV @ 0.349 + 2.232 V We then choose a convenient value for RCMP1 (5.62 kW) and solve Equation 37 for CCMP2: CCMP2 + TSS @ ICOMP (VCOMP * RCMP1 @ ICOMP) 30 mA (2.232 V * 5.62 kW @ 30 mA) + 6.5 ms @ + 0.0945 mF or 0.1 mF VTT VTT POWER GOOD 1−5 ms COMP/V CC CORE COMP Must Be < 0.27 V Before Powering Up POWER GOOD 50 ms Figure 28. Timing Diagram, VTT Power Good http://onsemi.com 30 CS5308 PACKAGE DIMENSIONS SO−28L DW SUFFIX CASE 751F−05 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBER PR5OTRUSION SHALL NOT BE 0.13 TOTATL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0_ 8_ − X− 28 D 15 E −Y− 1 PIN 1 IDENT 14 H 0.25 M Y M A 0.10 G B 0.025 M L C M DIM A A1 B C D E G H L M A1 Y S −T− SEATING PLANE TX S V2 is a trademark of Switch Power, Inc. Pentium is a registered trademark of Intel, Corp. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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