CS8129YDW16G

CS8129 5.0 V, 750 mA Low Dropout Linear Regulator with Lower RESET Threshold The CS8129 is a precision 5.0 V linear regulator capable of sourcing 750 mA. The RESET threshold voltage has been lowered to 4.2 V so that the regulator can be used with 4.0 V microprocessors. The lower RESET threshold also permits operation under low battery conditions (5.5 V plus a diode). The RESET’s delay time is externally programmed using a discrete RC network. During powerup, or when the output goes out of regulation, RESET remains in the low state for the duration of the delay. This function is independent of the input voltage and will function correctly as long as the output voltage remains at or above 1.0 V. Hysteresis is included in the Delay and the RESET comparators to improve noise immunity. A latching discharge circuit is used to discharge the delay capacitor when it is triggered by a brief fault condition. The regulator is protected against a variety of fault conditions: i.e. reverse battery, overvoltage, short circuit and thermal runaway conditions. The regulator is protected against voltage transients ranging from −50 V to +40 V. Short circuit current is limited to 1.2 A (typ). The CS8129 is packaged in a 16 lead surface mount package. Features • • • • • • • http://onsemi.com MARKING DIAGRAM 16 16 1 SO−16WB DW SUFFIX CASE 751G CS8129 AWLYYWWG 1 A WL YY, Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION 5.0 V ±3.0% Regulated Output Low Dropout Voltage (0.6 V @ 0.5 A) 750 mA Output Current Capability Reduced RESET Threshold for Use with 4.0 V Microprocessors Externally Programmed RESET Delay Fault Protection − Reverse Battery − 60 V, −50 V Peak Transient Voltage − Short Circuit − Thermal Shutdown These are Pb−Free Devices Device Package Shipping† CS8129YDW16G SO16WB (Pb−Free) 47 Units / Rail CS8129YDWR16G SO16WB (Pb−Free) 1000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 September, 2008 − Rev. 9 1 Publication Order Number: CS8129/D CS8129 PIN CONNECTIONS VIN NC NC GND GND RESET NC Delay 1 16 VOUT NC VOUT(SENSE) GND GND GND NC NC VIN Over Voltage Shutdown VOUT Regulated Supply for Circuit Bias Pre−Regulator Bandgap Reference − + Charge Current Generator Delay Error Amplifier Anti−Saturation and Current Limit VOUT (SENSE) Thermal Shutdown Latching Discharge − Q S + R − + VDISCHARGE RESET Delay Comparator + − GND Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS Rating Value Unit −0.5 to 26 V Internally Limited − −50, 60 V Internally Limited − 4.0 kV Junction Temperature −55 to +150 °C Storage Temperature Range −55 to +150 °C 260 peak 230 peak °C Input Operating Range Power Dissipation Peak Transient Voltage (46 V Load Dump @ 14 V VIN) Output Current Electrostatic Discharge (Human Body Model) Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 10 second maximum. 2. 60 seconds max above 183°C. http://onsemi.com 2 CS8129 ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 125°C, −40 ≤ TJ ≤ 150°C, 6.0 ≤ VIN ≤ 26 V, 5.0 mA ≤ IOUT ≤ 500 mA, RRESET = 4.7 kW to VOUT unless otherwise noted.) (Note 3) Characteristic Test Conditions Min Typ Max Unit − 4.85 5.0 5.15 V OUTPUT STAGE (VOUT) Output Voltage Dropout Voltage IOUT = 500 mA − 0.35 0.60 V Supply Current IOUT = 10 mA IOUT = 100 mA IOUT = 500 mA − − − 2.0 6.0 55 7.0 12 100 mA mA mA Line Regulation 6.0 V ≤ VIN ≤ 26 V, IOUT = 50 mA − 5.0 50 mV Load Regulation 50 mA ≤ IOUT ≤ 500 mA, VIN = 14 V − 10 50 mV Ripple Rejection f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA 54 75 − dB Current Limit − 0.75 1.20 − A Overvoltage Shutdown − 32 − 40 V Reverse Polarity Input Voltage DC VOUT ≥ −0.6 V, 10 W Load −15 −30 − V Thermal Shutdown Guaranteed by Design 150 180 210 °C Delay Charge Current VDELAY = 2.0 V 5.0 10 15 mA RESET Threshold VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF) 4.05 4.00 4.35 4.20 4.50 4.45 V V RESET Hysteresis VRH = VRT(ON) − VRT(OFF) 50 150 250 mV Delay Threshold Charge, VDC(HI) Discharge, VDC(LO) 3.25 2.85 3.50 3.10 3.75 3.35 V V 200 400 800 mV RESET AND DELAY FUNCTIONS Delay Hysteresis − RESET Output Voltage Low 1.0 V < VOUT < VRT(L), 3.0 kW to VOUT − 0.1 0.4 V RESET Output Leakage VOUT > VRT(H) Current − 0 10 mA Delay Capacitor Discharge Voltage Discharge Latched “ON”, VOUT > VRT − 0.2 0.5 V Delay Time CDELAY = 0.1 mF, (Note 4) 16 32 48 ms 3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. 4. Assuming ideal capacitor. CDelay VDelay Threshold Charge + CDelay 3.5 105 (typ) Delay Time + ICharge PACKAGE LEAD DESCRIPTION PACKAGE LEAD # SO−16WB LEAD SYMBOL FUNCTION 1 VIN 16 VOUT Regulated 5.0 V output. 4, 5, 11, 12, 13 GND Ground Connection. 8 Delay Timing capacitor for RESET function. 6 RESET 14 VOUT(SENSE) Unregulated supply voltage to IC. CMOS/TTL compatible output lead. RESET goes low whenever VOUT drops below 6.0% of it’s regulated value. Remote sensing of output voltage. http://onsemi.com 3 CS8129 TYPICAL PERFORMANCE CHARACTERISTICS 55 50 120 RLOAD = 25 W 40 35 30 ICQ. (mA) ICQ (mA) RLOAD = 6.67 W 100 45 125°C 25 20 15 1 2 60 RLOAD = 10 W 20 −40°C 5 0 80 40 25°C 10 0 Room Temp 3 4 5 6 7 8 9 0 10 RLOAD = 25 W RLOAD = NO LOAD 0 1 2 3 4 VIN (V) 4.5 4.5 4.0 4.0 3.5 3.5 3.0 125°C 2.5 2.0 1.0 10 RLOAD = 6.67 W 3.0 RLOAD = NO LOAD 2.5 2.0 0 1 2 3 RLOAD = 10 W 0.5 4 5 6 7 8 9 0 10 0 1 2 3 VIN (V) Figure 4. Output Voltage vs. Input Voltage Over Temperature 100 80 Load Regulation (mV) 40 TEMP = 25°C 20 TEMP = −40°C 0 −20 TEMP = 125°C −60 5 VIN (V) 40 20 200 8 9 10 TEMP = 25°C 0 VIN = 14 V −20 −40 TEMP = 125°C −80 100 7 TEMP = −40°C 60 −60 −80 0 6 100 60 −40 4 Figure 5. VOUT vs. VIN Over RLOAD VIN = 6−26 V 80 Line Reg. (mV) 9 1.0 −40°C 25°C 0.5 −100 8 1.5 1.5 0 7 Room Temp 5.0 VOUT (V) VOUT (V) 5.5 RLOAD = 25 W 5.0 6 Figure 3. Quiescent Current vs. Input Voltage Over Load Resistance Figure 2. Quiescent Current vs. Input Voltage Over Temperature 5.5 5 VIN (V) 300 400 500 600 700 −100 800 0 100 200 300 400 500 600 700 800 Output Current (mA) Output Current (mA) Figure 6. Line Regulation vs. Output Current Figure 7. Load Regulation vs. Output Current http://onsemi.com 4 900 800 100 90 700 80 Quiescent Current (mA) Dropout Voltage (mV) CS8129 25°C 600 500 125°C 400 300 −40°C 200 100 0 70 50 40 30 20 −40°C 10 0 100 200 300 400 500 600 700 0 800 200 300 400 500 101 ESR (ohms) 60 50 Stable Region 100 CO = 47 mF 10−2 20 100 101 VOUT VRT(ON) VRT(OFF) 102 103 104 105 106 CO = 68 mF 10−3 COUT = 10 mF, ESR = 1.0 W 10 107 10−4 108 100 101 102 Frequency (Hz) Output Current (mA) Figure 10. Ripple Rejection Figure 11. Output Capacitor ESR VRH RESET 103 (1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max: RESET Voltage (1.0 V) (1) (3) (2) VRL tDELAY DELAY VDH VDC(HI) VDC(LO) 800 CO = 47/68 mF 10−1 COUT = 10 mF, ESR = 1.0 W 30 700 102 70 40 600 103 COUT = 10 mF, ESR = 1.0 & 0.1 mF, ESR = 0 80 100 Figure 9. Quiescent Current vs. Output Current IOUT = 250 mA 90 0 Output Current (mA) Figure 8. Dropout Voltage vs. Output Current Rejection (dB) 25°C 125°C 60 Output Current (mA) 0 VIN = 14 V (2) VDIS Figure 12. RESET Circuit Waveform http://onsemi.com 5 CS8129 CIRCUIT DESCRIPTION The CS8129 RESET function has hysteresis on both the reset and delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1.0 V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Block Diagram on page 2). condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDC(HI). VOUT VIN CIN* 100 nF Low Voltage Inhibit Circuit Delay This circuit monitors output voltage, and when output voltage is below the specified minimum causes the RESET output transistor to be in the ON (saturation) state. When the output voltage is above the specified level, this circuit permits the RESET output transistor to go into the OFF state if allowed by the RESET Delay circuit. RRST 4.7 kW CS8129 COUT** 10 mF to 100 mF RESET GND Delay 0.1 mF *CIN is required if regulator is far from the power source filter. **COUT is required for stability. Reset Delay Circuit Figure 13. Test & Application Circuit This circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the “Low Voltage Inhibit” circuit indicates that output voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage is below VRT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures that a controlled RESET pulse is generated following detection of an error The Delay time for the RESET function is calculated from the formula: Delay time + CDelay VDelay Threshold ICharge Delay time + CDelay(mF) 3.2 105 If CDelay = 0.1 mF, Delay time (ms) = 32 ms ±50%: i.e. 16 ms to 48 ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. APPLICATION NOTES STABILITY CONSIDERATIONS connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. The output or compensation capacitor helps determine three main characteristics of a linear regulator: start−up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 13 should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box http://onsemi.com 6 CS8129 Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. IIN Figure 14. Single Output Regulator With Key Performance Parameters Labeled HEAT SINKS A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA. The maximum power dissipation for a single output regulator (Figure 14) is: (1) RqJA + RqJC ) RqCS ) RqSA where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: 150C * TA PD VOUT IQ CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR RqJA + IOUT Control Features Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. PD(max) + NJVIN(max) * VOUT(min)NjIOUT(max) ) VIN(max)IQ SMART REGULATOR® VIN (3) where: RqJC = the junction−to−case thermal resistance, RqCS = the case−to−heatsink thermal resistance, and RqSA = the heatsink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. (2) The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 WB CASE 751G ISSUE E 1 SCALE 1:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* 16 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 1 XXXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42567B SOIC−16 WB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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