DM74ALS125MX

Revised February 2000 DM74ALS125 Quad 3-STATE Buffer General Description Features This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. The 3-STATE circuitry contains a feature that maintains the buffer outputs in 3-STATE (high impedance state) during power supply ramp-up or rampdown. This eliminates bus glitching problems that arise during power-up and power-down. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs. ■ Advanced low power Schottky TTL process oxide-isolated ion-implanted ■ Functional and pin compatible with the 74LS counterpart ■ Switching response specified into 500Ω and 50 pF load ■ Switching response specifications guaranteed over full temperature and VCC supply range ■ PNP input design reduces input loading ■ Low level drive current: 74ALS = 24 mA Ordering Code: Order Number Package Number Package Description DM74ALS125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS125N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Diagram Functional Table Y=A Input Output A C L L Y L H L H X H Hi-Z H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level Hi-Z = 3-STATE (Outputs are disabled) © 2000 Fairchild Semiconductor Corporation DS010620 www.fairchildsemi.com DM74ALS125 Quad 3-STATE Buffer November 1989 DM74ALS125 Absolute Maximum Ratings(Note 1) Supply Voltage, VCC 7V Input Voltage 7V Voltage Applied to Disabled Output 5.5V Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 0 to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Typical θJA N Package 78.0°C/W M Package 111.0°C/W Recommended Operating Conditions Symbol Parameter Min Typ Max 4.5 5 5.5 Units VCC Supply Voltage VIH HIGH Level Input Voltage V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −15 mA IOL LOW Level Output Current 24 mA TA Operating Free-Air Temperature 70 °C 2 V 0 Electrical Characteristics over recommended operating free air temperature (unless otherwise specified) Symbol Parameter Conditions VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA VOH HIGH Level VCC = 4.5V to 5.5V IOH = −0.4 mA Output Voltage VCC = 4.5V IOH = −3 mA IOH = Max VOL LOW Level VCC = 4.5V Input Current at Max Input Voltage IIH HIGH Level Input Current IIL LOW Level Input Current IO Output Drive Current IOZH HIGH Level 3-STATE Output Current IOZL LOW Level 3-STATE Output Current ICC Supply Current Max Units −1.5 V VCC − 2 V 2.4 V 2 V IOL = 12 mA 0.25 0.4 0.35 0.5 V VCC = 5.5V, VI = 7V 0.1 mA VCC = 5.5V, VI = 2.7V 20 µA VCC = 5.5V, VIL = 0.4V −0.1 mA −112 mA VCC = 5.5V, VO = 2.7V 20 µA VCC = 5.5V, VO = 0.4V −20 µA VCC = 5.5V, VO = 2.25V VCC = 5.5V −30 V Outputs HIGH 7 10 mA Outputs LOW 10 14 mA 13.5 18 mA 3-STATE www.fairchildsemi.com Typ IOL = 24 mA Output Voltage II Min 2 Symbol tPLH Parameter Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPZH Output Enable Time to HIGH Level Output tPZL Output Enable Time to LOW Level Output tPHZ Output Disable Time from HIGH Level Output tPLZ Output Disable Time from LOW Level Output From To (Input) (Output) A Y A Y C Y C Conditions VCC = 4.5V to 5.5V, Min Units Max 3 10 ns 2 10 ns 2 13 ns Y 2 12 ns C Y 1 8 ns C Y 2 13 ns 3 CL = 50 pF, R1 = 500Ω, R2 = 500Ω, TA = Min to Max www.fairchildsemi.com DM74ALS125 Switching Characteristics DM74ALS125 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M14A www.fairchildsemi.com 4 DM74ALS125 Quad 3-STATE Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com