DM74ALS169BMX

Revised April 2000 DM74ALS169B Synchronous Four-Bit Up/Down Counters General Description Features These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74ALS169B is a four-bit binary up/ down counter. The carry output is decoded to prevent spikes during normal mode of counting operation. Synchronous operation is provided so that outputs change coincident with each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive going) edge of clock input waveform. ■ Switching specifications at 50 pF These counters are fully programmable; that is, the outputs may each be preset either HIGH or LOW. The load input circuitry allows loading with carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. ■ Switching specifications guaranteed over full temperature and VCC range ■ Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Functionally and pin-for-pin compatible with Schottky and low power Schottky TTL counterpart ■ Improved AC performance over Schottky and low power Schottky counterparts ■ Synchronously programmable ■ Internal look ahead for fast counting ■ Carry output for n-bit cascading ■ Synchronous counting ■ ESD inputs The carry look-ahead circuitry permits cascading counters for n-bit synchronous applications without additional gating. Both count enable inputs (P and T) must be LOW to count. The direction of the count is determined by the level of the up/down input. When the input is HIGH, the counter counts UP; when LOW, it counts DOWN. Input T is fed forward to enable the carry outputs. The carry output thus enabled will produce a low level output pulse with a duration approximately equal to the high portion of the QA output when counting UP, and approximately equal to the low portion of the QA when counting DOWN. This low level overflow carry pulse can be used to enable successively cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. The control functions for these counters are fully synchronous. Changes at control inputs (enable P, enable T, load, up/down) which modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading or counting) will be dictated solely by the conditions meeting the stable setup and hold times. Ordering Code: Order Number Package Number DM74ALS169BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Description DM74ALS169BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation DS006207 www.fairchildsemi.com DM74ALS169B Synchronous Four-Bit Up/Down Counters April 1984 DM74ALS169B Connection Diagram Mode Select Table EP ET U/D L X X X Load (Pn → Qn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold) State Diagram www.fairchildsemi.com Action on Rising LOAD 2 Clock Edge DM74ALS169B Logic Diagram 3 www.fairchildsemi.com DM74ALS169B Absolute Maximum Ratings(Note 1) Supply Voltage 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. −65°C to +150°C Storage Temperature Range Typical θJA N Package 78.1°C/W M Package 106.8°C/W Recommended Operating Conditions Symbol Parameter Min Nom Max 4.5 5 5.5 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current fCLK Clock Frequency tSU Setup Time (Note 2) 2 0 Data; Hold Time (Note 2) ns En P, En T 15↑ 8 ns Load 15↑ 8 ns U/D 15↑ 10 ns 0↑ −3 ns En P, En T 0↑ −3 ns Load 0↑ −4 ns U/D 0↑ −4 Data; Width of Clock Pulse 13 Note 2: The symbol (↑) indicates that the rising edge of the clock is used as reference. www.fairchildsemi.com mA MHz 6 A, B, C, D tW 8 40 15↑ A, B, C, D tH V V 4 ns ns over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C Symbol Parameter Conditions VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA VOH HIGH Level IOH = −0.4 mA Output Voltage VCC = 4.5V to 5.5V VOL LOW Level Output Voltage II Input Current @ Max Input Voltage Min Typ Max Units −1.5 V VCC − 2 VCC = 4.5V IOL = 8 mA V 0.35 VCC = 5.5V, VIH = 7V 0.5 V 0.1 mA IIH HIGH Level Input Current VCC = 5.5V, VIH = 2.7V 20 µA IIL LOW Level Input Current VCC = 5.5V, VIL = 0.4V −0.2 mA IO Output Drive Current VCC = 5.5V, VO = 2.25V ICC Supply Current VCC = 5.5V −30 −112 mA 15 25 mA Min Max Units Switching Characteristics over recommended operating free air temperature range Symbol Parameter Conditions fMAX Maximum Clock Frequency tPLH Propagation Delay Time VCC = 4.5V to 5.5V LOW-to-HIGH Level Output RL = 500Ω Propagation Delay Time CL = 50 pF tPHL From 40 HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL To Propagation Delay Time HIGH-to-LOW Level Output MHz Clock Ripple Carry 3 20 ns Clock Ripple Carry 6 20 ns Clock Any Q 2 15 ns Clock Any Q 5 20 ns En T Ripple Carry 2 13 ns En T Ripple Carry 3 16 ns U/D (Note 3) Ripple Carry 5 19 ns U/D (Note 3) Ripple Carry 5 19 ns Note 3: Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If the count is maximum, the ripple carry output will be out of phase. 5 www.fairchildsemi.com DM74ALS169B Electrical Characteristics DM74ALS169B Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 6 DM74ALS169B Synchronous Four-Bit Up/Down Counters Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com