0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
DM74ALS540ASJX

DM74ALS540ASJX

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    SOIC20_200MIL

  • 描述:

    IC BUFFER INVERT 5.5V 20SOP

  • 数据手册
  • 价格&库存
DM74ALS540ASJX 数据手册
Revised February 2000 DM74ALS540A Octal Inverting Buffer and Line Driver with 3-STATE Outputs General Description Features This octal buffer and line driver is designed to have the performance of the DM74ALS240A series and, at the same time, offer a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly enhances printed circuit board layout. The 3-STATE control gate is a 2-input NOR such that if either G1 or G2 is HIGH, all eight outputs are in the high impedance state. ■ Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Switching performance is guaranteed over full temperature and VCC supply range ■ Data flow-thru pinout (All inputs on opposite side from outputs) ■ P-N-P inputs reduce DC loading Ordering Code: Order Number Package Number Package Description DM74ALS540AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS540ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS540AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Output G1 G2 A Y H X X Hi-Z X H X Hi-Z L L L H L L H L H = HIGH Logic Level L = LOW Logic Level X = Don't Care (Either HIGH or LOW Logic Level) Hi-Z = High Impedance (OFF) State © 2000 Fairchild Semiconductor Corporation DS009170 www.fairchildsemi.com DM74ALS540A Octal Inverting Buffer and Line Driver with 3-STATE Outputs October 1986 DM74ALS540A Absolute Maximum Ratings(Note 1) Supply Voltage 7V Input Voltage 7V Voltage Applied to a Disabled 3-STATE Output 5.5V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 0°C to +70°C Operating Free-Air Temperature Range −65°C to +150°C Storage Temperature Range Typical θJA N Package 58.5°C/W M Package 77.5°C/W Recommended Operating Conditions Symbol Parameter Min Nom Max Units 4.5 5 5.5 V VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.7 V IOH HIGH Level Output Current −15 mA IOL LOW Level Output Current 24 mA TA Free Air Operating Temperature 70 °C 2 V 0 Electrical Characteristics over recommended free air temperature range Symbol Parameter Test Conditions Min VIK Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = 4.5V to 5.5V IOH = −0.4 mA Output Voltage VCC = Min IOH = −3 mA VCC = Min LOW Level Output Voltage Max Units −1.5 V VCC − 2 2.4 IOH = Max VOL Typ 3.2 V 2 IOL = 12 mA 0.25 0.4 IOL = 24 mA 0.35 0.5 mA II Input Current @ Maximum Input Voltage VCC = Max, VI = 7V 100 µA IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −100 µA IOZH HIGH Level 3-STATE Output Current VCC = Max, VO = 2.7V 20 µA IOZL LOW Level 3-STATE Output Current VCC = Max, VO = 0.4V −20 µA IO Output Drive Current VCC = Max, VO = 2.25V −112 mA ICC Supply Current VCC = Max −30 Outputs HIGH 5 10 Outputs LOW 13 22 Outputs Disabled 11 19 mA Switching Characteristics over recommended free air operating temperature range Symbol tPLH tPHL Parameter Conditions Propagation Delay Time VCC = 4.5V to 5.5V, LOW-to-HIGH Level Output R1 = R2 = 500Ω, Propagation Delay Time CL = 50 pF HIGH-to-LOW Level Output From (Input) Min Max Units A or B to Y 2 12 ns A or B to Y 2 9 ns To (Output) tPZH Output Enable Time to HIGH Level Output G to Y 5 15 ns tPZL Output Enable Time to LOW Level Output G to Y 8 20 ns tPHZ Output Disable Time from HIGH Level Output G to Y 1 10 ns tPLZ Output Disable Time from LOW Level Output G to Y 2 12 ns www.fairchildsemi.com 2 DM74ALS540A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 3 www.fairchildsemi.com DM74ALS540A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 4 DM74ALS540A Octal Inverting Buffer and Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com
DM74ALS540ASJX 价格&库存

很抱歉,暂时无法提供与“DM74ALS540ASJX”相匹配的价格&库存,您可以联系我们找货

免费人工找货