DM74ALS563AN

Revised February 2000 DM74ALS563A Octal D-Type Transparent Latch with 3-STATE Output General Description Features These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. ■ Switching specifications at 50 pF ■ Switching specifications guaranteed over full temperature and VCC range ■ Advanced oxide-isolated, ion-implanted Schottky TTL process ■ 3-STATE buffer-type outputs drive bus lines directly The eight inverting latches of the DM74ALS563A are transparent D-type latches. While the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the complement of the level of the data that was set up. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches. That is, the old data can be retained or new data can be entered even while the outputs are OFF. Ordering Code: Order Number Package Number DM74ALS563AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Description DM74ALS563AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation DS009162 www.fairchildsemi.com DM74ALS563A Octal D-Type Transparent Latch with 3-STATE Output October 1986 DM74ALS563A Function Table Logic Diagram Output Enable Control G D Output L H H L L H L H Q L L X Q0 H X X Z L = LOW State H = HIGH State X = Don’t Care Z = High Impedance State Q0 = Previous Condition of Q www.fairchildsemi.com 2 Supply Voltage 7V Input Voltage 7V Voltage Applied to Disabled Output 5.5V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Typical θJA N Package 56.0°C/W M Package 75.0°C/W Recommended Operating Conditions Symbol Parameter Min Nom Max Units 4.5 5 5.5 V VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −2.6 mA 24 mA IOL LOW Level Output Current tW Width of Enable Pulse, HIGH or LOW tSU 2 V 15 ns Data Setup Time (Note 2) 10↓ ns tH Data Hold Time (Note 2) 10↓ TA Free Air Operating Temperature ns 0 °C 70 Note 2: The (↓) arrow indicates the negative edge of the enable is used for reference. Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C. Symbol Parameter Conditions VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA VOH HIGH Level VCC = 4.5V Output Voltage VIL = VIL Max VOL Min IOH = Max 2.4 Typ Max Units −1.2 V 3.2 V VCC = 4.5V to 5.5V IOH = −400 µA LOW Level VCC = 4.5V IOL = 12 mA VCC − 2 0.25 0.4 Output Voltage VIH = 2V IOL = 24 mA 0.35 0.5 V 0.1 mA V V II Input Current @ Maximum IIH HIGH Level Input Current VCC = 5.5V, VIH = 2.7V 20 µA IIL LOW Level Input Current VCC = 5.5V, VIL = 0.4V −0.1 mA IO Output Drive Current VCC = 5.5V, VO = 2.25V −112 mA IOZH OFF-State Output Current VCC = 5.5V, VIH = 2V HIGH Level Voltage Applied VO = 2.7V 20 µA −20 µA Input Voltage IOZL ICC VCC = 5.5V, VIH = 7V OFF-State Output Current VCC = 5.5V, VIH = 2V LOW Level Voltage Applied VO = 0.4V Supply Current −30 VCC = 5.5V Outputs HIGH 10 17 mA Outputs OPEN Outputs LOW 16 26 mA Outputs Disabled 17 29 mA 3 www.fairchildsemi.com DM74ALS563A Absolute Maximum Ratings(Note 1) DM74ALS563A Switching Characteristics over recommended operating free air temperature range Symbol tPLH tPHL Parameter Conditions Propagation Delay Time VCC = 4.5V to 5.5V LOW-to-HIGH Level Output RL = 500Ω Propagation Delay Time CL = 50 pF From HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPZH tPZL tPHZ tPLZ To Min Max Units Data Any Q 3 18 ns Data Any Q 3 14 ns Enable Any Q 8 22 ns Enable Any Q 8 21 ns Any Q 4 18 ns Any Q 4 18 ns Any Q 2 10 ns Any Q 3 15 ns Output Enable Time Output to HIGH Level Output Control Output Enable Time Output to LOW Level Output Control Output Disable Time Output from HIGH Level Output Control Output Disable Time Output from LOW Level Output Control www.fairchildsemi.com 4 DM74ALS563A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com DM74ALS563A Octal D-Type Transparent Latch with 3-STATE Output Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6