DM74AS280N

Revised March 2000 DM74AS280 9-Bit Parity Generator/Checker General Description Features These universal, 9-bit parity generators/checkers utilize advanced Schottky high performance circuitry and feature odd/even outputs to facilitate operation of either odd or even parity applications. The word length capability is easily expanded by cascading. ■ Generates either odd or even parity for nine data lines The DM74AS280 can be used to upgrade the performance of most systems utilizing the ’180 parity generator/checker. Although the DM74AS280 is implemented without expander inputs, the corresponding function is provided by the availability of an input at pin 4 and no internal connection at pin 3. This permits the DM74AS280 to be substituted for the ’180 in existing designs to produce identical function even if DM74AS280s are mixed with existing ’180s. ■ Inputs are buffered to lower the drive requirements ■ Can be used to upgrade existing systems using MSI parity circuits ■ Cascadable for N-bits ■ Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Switching specifications at 50 pF ■ Switching specifications guaranteed over full temperature and VCC range Ordering Code: Order Number Package Number Package Description DM74AS280M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74AS280N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Number of Inputs (A thru I) Outputs that are HIGH ∑Even 0, 2, 4, 6, 8 H ∑Odd L 1, 3, 5, 7, 9 L H L = LOW State H = HIGH State © 2000 Fairchild Semiconductor Corporation DS006303 www.fairchildsemi.com DM74AS280 9-Bit Parity Generator/Checker October 1986 DM74AS280 Logic Diagram www.fairchildsemi.com 2 Supply Voltage 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. −65°C to +150°C Storage Temperature Range Typical θJA N Package 77.0°C/W M Package 108.0°C/W Recommended Operating Conditions Symbol Parameter Min Typ Max 4.5 5 5.5 Units VCC Supply Voltage VIH HIGH Level Input Voltage V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −2 mA IOL LOW Level Output Current 20 mA TA Free-Air Operating Temperature 70 °C 2 V 0 Electrical Characteristics Over recommended free-air temperature range. All typical values are measured at VCC = 5V, TA = 25°C. Symbol Parameter Conditions Min Max Units −1.2 V 0.5 V VCC = 5.5V, VIH = 7V 0.1 mA VCC = 5.5V, VIH = 2.7V 20 µA −0.5 mA VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA VOH HIGH Level Output Voltage IOH = −2 mA, VCC = 4.5V to 5.5V VOL LOW Level Output Voltage VCC = 4.5V, IOL = Max II Input Current @ Max Input Voltage IIH HIGH Level Input Current IIL LOW Level Input Current VCC = 5.5V, VIL = 0.4V IO Output Drive Current VCC = 5.5V, VO = 2.25V ICC Supply Current VCC = 5.5V Typ VCC − 2 V 0.35 −30 −112 mA 25 40 mA Switching Characteristics over recommended operating free air temperature range Symbol tPLH tPHL Parameter Conditions Propagation Delay Time, VCC = 4.5V to 5.5V, LOW-to-HIGH Level Output CL = 50 pF, Propagation Delay Time, RL = 500Ω From To Min Max Units Data ∑Even 3 12 ns 3 11 ns 3 12 ns 3 11.5 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time, Data LOW-to-HIGH Level Output tPHL Propagation Delay Time, HIGH-to-LOW Level Output 3 ∑Odd www.fairchildsemi.com DM74AS280 Absolute Maximum Ratings(Note 1) DM74AS280 Typical Applications Three DM74AS280s can be used to implement a 25-line parity generator/checker. input (S135) exclusive-OR gate for 18 or 27-line parity applications. As an alternative, the outputs of two or three parity generators/checkers can be decoded with a 2-input (AS86) or 3- Longer word lengths can be implemented by cascading DM74AS280s. As shown in Figure 2, parity can be generated for word lengths up to 81 bits. FIGURE 1. 25-Line Parity/Generator Checker FIGURE 2. 81-Line Parity/Generator Checker www.fairchildsemi.com 4 DM74AS280 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M14A 5 www.fairchildsemi.com DM74AS280 9-Bit Parity Generator/Checker Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6