Revised April 2000
DM74AS286
9-Bit Parity Generator/Checker
with Bus-Driver Parity I/O Port
General Description
Features
These universal, 9-bit parity generators/checkers utilize
advanced Schottky high performance circuitry and feature
odd/even outputs to facilitate operation of either odd or
even parity applications. The word length capability is easily expanded by cascading.
■ PNP inputs to reduce bus loading
The DM74AS286 can be used to upgrade the performance
of most systems utilizing the DM74AS280 parity generator/
checker. Although the DM74AS286 is implemented without
expander inputs, the corresponding function is provided by
the availability of an input pin XMIT. XMIT is a control line
which makes parity error output active and parity an input
port when HIGH; when LOW, parity error output is inactive
and parity becomes an output port. In addition, parity I/O
control circuitry contains a feature to keep the I/O port in
the 3-STATE during power UP or DOWN to prevent bus
glitches.
■ Generates either odd or even parity for nine data lines
■ Inputs are buffered to lower the drive requirements
■ Can be used to upgrade existing systems using MSI
parity circuits
■ Cascadable for n-bits
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full
temperature and VCC range
■ A parity I/O portable to drive bus
Ordering Code:
Order Number
Package Number
Package Description
DM74AS286M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74AS286N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Number of Inputs
Parity I/O
(A thru I)
that are HIGH
Parity
XMIT Error
Input Output
Mode
of
Operation
0, 2, 4, 6, 8
N/A
H
L
H
Parity
1, 3, 5, 7, 9
N/A
L
L
H
Generator
0, 2, 4, 6, 8
H
N/A
H
H
Parity
0, 2, 4, 6, 8
L
N/A
H
L
Checker
1, 3, 5, 7, 9
H
N/A
H
L
Parity
1, 3, 5, 7, 9
L
N/A
H
H
Checker
L = LOW Logic Level
H = HIGH Logic Level
N/A = Not Applicable
© 2000 Fairchild Semiconductor Corporation
DS006305
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DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port
October 1986
DM74AS286
Absolute Maximum Ratings(Note 1)
Supply Voltage
7V
Input Voltage
7V
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
0°C to +70°C
Operating Free Air Temperature Range
−65°C to +150°C
Storage Temperature Range
Typical θJA
N Package
77.0°C/W
M Package
108.0°C/W
Recommended Operating Conditions
Symbol
Parameter
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
IOH
HIGH Level Output Current
IOL
LOW Level Output Current
TA
Min
Typ
Max
4.5
5
5.5
Units
V
2
V
0.8
V
−15
mA
Parity Error
−2
mA
Parity I/O
48
mA
Parity Error
20
mA
70
°C
Parity I/O
Operating Free-Air Temperature
0
Electrical Characteristics
over recommended free-air temperature range. All typical values are measured at VCC = 5V, T A = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
VIK
Input Clamp Voltage
VCC = 4.5V, IIN = −18 mA
VOH
HIGH Level
IOH = Max, VCC = 4.5V
Output Voltage
VCC = 4.5V to 5.5V, IOH = −2 mA
VOL
LOW Level Output Voltage
VCC = 4.5V, IOL = Max
II
Input Current at Maximum
VCC = 5.5V, VIH = 7V
Input Voltage
(VI = 5.5V for Parity I/O)
HIGH Level Input Current
VCC = 5.5V
Others
20
VIH = 2.7V (Note 2)
Parity I/O
50
IIH
−1.2
2.4
IIL
LOW Level Input Current
VCC = 5.5V, VIL = 0.4V (Note 2)
Output Drive Current
VCC = 5.5V, VOUT = 2.25V
ICC
Supply Current
VCC = 5.5V, Transmit Mode
XMIT = LOW
Receive Mode
XMIT = HIGH
Note 2: For I/O ports, the parameters IIH and IIL include the OFF-state current, IOZH and IOZL.
2
−30
V
V
VCC − 2
V
0.35
IO
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3.2
Units
0.5
V
0.1
mA
µA
−0.5
mA
−112
mA
43
mA
50
mA
over recommended supply and temperature range
Symbol
Parameter
tPLH
Propagation Delay Time
from LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
from HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
from LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
from HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
from LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
from HIGH-to-LOW Level Output
From
To
Min
Max
Units
Any Data Input
Parity I/O
3
15
ns
Any Data Input
Parity I/O
3
14
ns
Any Data Input
Parity Error
3
16.5
ns
Any Data Input
Parity Error
3
16.5
ns
Parity I/O
Parity Error
3
9
ns
Parity I/O
Parity Error
3
9
ns
tPZL
Output Enable Time to LOW Level
XMIT
Parity I/O
3
16
ns
tPLZ
Output Disable Time from LOW Level
XMIT
Parity I/O
3
10
ns
tPZH
Output Disable Time from HIGH Level
XMIT
Parity I/O
3
13
ns
tPHZ
Output Enable Time to HIGH Level
XMIT
Parity I/O
3
11.5
ns
Typical Applications
Number of
Parity
Inputs that
Result
are Logic “1”
Output
0, 2, 4, 6, 8, 10
Even
L
1, 3, 5, 7, 9
Odd
H
FIGURE 1. Dedicated 10-Bit Parity Sensing Configuration
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DM74AS286
Switching Characteristics
DM74AS286
Typical Applications
(Continued)
Direction
I/O
Control
Direction
(XMIT)
(Parity I/O)
Level
H
Input
H
True
(Receive)
L
False
Output
H
N/A
L
Parity Check Result
(Parity Error)
(Transmit)
Parity Select
(Input I)
Level
Format
H
Even
L
Odd
L = LOW Logic Level
H = HIGH Logic Level
N/A = Not Applicable
FIGURE 2. Bus I/O Parity Implementation
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4
∑ Result
DM74AS286
Typical Applications
(Continued)
Note: Parity format in this configuration is “odd parity”
FIGURE 3. 90-Bit Parity Generator/Checker Implementation
Using Device Expansion Techniques
5
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DM74AS286
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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6
DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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