DM74AS652WM

Revised July 2003 DM74AS651 • DM74AS652 Octal Bus Transceiver and Register General Description Features These devices incorporate an octal transceiver and an octal D-type register configured to enable transmission of data from bus to bus or internal register to bus. The DM74AS651 offers 64-Industrial grade product guaranteeing performance from −40°C to +85°C. ■ Switching specifications at 50 pF These bus transceivers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these devices with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. ■ Switching specifications guaranteed over full temperature and VCC range ■ Advanced oxide-isolated, ion-implanted Schottky TTL process ■ 3-STATE buffer-type outputs drive bus lines directly ■ Guaranteed performance over industrial temperature range (−40°C to +85°C) in 64-grade products The registers in the DM74AS651 and DM74AS652 are edge-triggered D-type flip-flops. On the positive transition of the clock (CAB or CBA), the input data is stored. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data. The Enable (GAB and GBA) control pins provide four modes of operation; real-time data transfer from bus A-toB, real-time data transfer from bus B-to-A, real-time bus A and/or B data transfer to internal storage, or internal stored data transfer to bus A and/or B. Ordering Code: Order Number Package Number DM74AS651WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Description DM74AS651NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide DM74AS652WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide DM74AS652NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2003 Fairchild Semiconductor Corporation DS006325 www.fairchildsemi.com DM74AS651 • DM74AS652 Octal Bus Transceiver and Register October 1986 DM74AS651 • DM74AS652 Connection Diagram Function Table INPUTS GAB GBA CAB L H L H ↑ L L X CBA H or L H or L DATA I/O (Note 1) SAB SBA X X ↑ X X X X L A1 B1 THRU THRU A8 B8 Input Input Output OPERATION OR FUNCTION DM74AS651 DM74AS652 Isolation Isolation Store A and B Data Store A and B Data Input Real Time B Data to A Bus Real Time B Data to A Bus Output L L X H or L X H Stored B Data to A Bus Stored B Data to A Bus H H X X L X Real Time A Data to B Bus Real Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus Input H H H or L H L X H ↑ H H L L X H or L H or L H X H H Output Output H or L X X Input ↑ ↑ X (Note 2) X Input Output X H or L ↑ X X Unspecified (Note 1) L ↑ ↑ X X (Note 2) Output & Stored B Data to A Bus & Stored B Data to A Bus Unspecified Store A, Hold B (Note 1) Store A, Hold B Store A in both registers Store A in both registers Input Hold A, Store B Hold A, Store B Input Store B in both registers Store B in both registers H = HIGH Level L = LOW Level X = Irrelevant ↑ = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Note 2: If the select control is LOW, the clocks can occur simultaneously. If the select control is HIGH, the clocks must be staggered in order to load both registers. www.fairchildsemi.com 2 DM74AS651 • DM74AS652 Logic Diagrams DM74AS651 DM74AS652 Schematics of Inputs and Outputs Equivalent of All Other Inputs Typical of All DM74AS651, DM74AS652 Outputs 3 www.fairchildsemi.com DM74AS651 • DM74AS652 Absolute Maximum Ratings(Note 3) Supply Voltage 7V Input Voltage Control Inputs 7V I/O Ports 5.5V 0°C to +70°C Operating Free Air Temperature Range Note 3: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. −65°C to +150°C Storage Temperature Range Typical θJA N Package 41.1°C/W M Package 81.5°C/W Recommended Operating Conditions Symbol Parameter Min Nom Max 4.5 5 5.5 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −15 mA IOL LOW Level Output Current fCLK Clock Frequency tWCLK Width of Enable Pulse V 2 V 0 HIGH 5 LOW 6 48 mA 90 MHz ns tSU Data Setup Time 6 ns tH Data Hold Time 0 ns TA Operating Free Air Temperature 0 °C 70 Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C. Symbol Parameter Conditions Min Typ VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA VOH HIGH Level VCC = 4.5V IOH = Max IOH = −3 mA 2.4 VCC = 4.5V to 5.5V IOH = −2 mA VCC − 2 Output Voltage VOL LOW Level Output Voltage VCC = 4.5V, IOL = Max II Input Current at VCC = 5.5V Max Input Voltage IIH IIL Max Units −1.2 V 2 3.2 0.35 V 0.5 VI = 7V Control Inputs 0.1 VI = 5.5V A or B Ports 0.1 HIGH Level VCC = 5.5V, Control Inputs 20 Input Current VIH = 2.7V A or B Ports 70 LOW Level VCC = 5.5V, Control Inputs −0.5 Input Current VIL = 0.4V A or B Ports −0.75 IO Output Drive Current VCC = 5.5V, VO = 2.25V ICC Supply Current VCC = 5.5V −30 DM74AS651 DM74AS652 www.fairchildsemi.com 4 −112 Outputs HIGH 110 185 Outputs LOW 120 195 Outputs Disabled 130 195 Outputs HIGH 120 195 Outputs LOW 130 211 Outputs Disabled 130 211 V mA µA mA mA mA Symbol Parameter Conditions fMAX Maximum Clock Frequency VCC = 4.5V to 5.5V tPLH Propagation Delay Time R1 = R2 = 500Ω LOW-to-HIGH Level Output CL = 50 pF tPHL From To CBA or CAB Propagation Delay Time A or B Propagation Delay Time Propagation Delay Time LOW-to-HIGH Level Output tPHL SBA or SAB Propagation Delay Time A or B (Note 4) HIGH-to-LOW Level Output tPZH Output Enable Time to HIGH Level Output tPZL Output Enable Time to LOW Level Output tPHZ Enable GBA A Output Disable Time from HIGH Level Output tPLZ Output Disable Time from LOW Level Output tPZH Output Disable Time to HIGH Level Output tPZL Output Disable Time to LOW Level Output tPHZ Enable GAB Output Disable Time 8.5 ns 2 9 ns 2 8 ns 1 7 ns 2 11 ns 2 9 ns 2 10 ns 3 16 ns 2 9 ns 2 9 ns 3 11 ns 3 16 ns 2 10 ns 2 11 ns B from HIGH Level Output tPLZ MHz 2 B or A HIGH-to-LOW Level Output tPLH Units A or B Propagation Delay Time LOW-to-HIGH Level Output tPHL Max 90 HIGH-to-LOW Level Output tPLH Min Output Disable Time from LOW Level Output Note 4: These parameters are measured with the internal output state of the storage register opposite to that of the bus input. 5 www.fairchildsemi.com DM74AS651 • DM74AS652 DM74AS651 Switching Characteristics DM74AS651 • DM74AS652 DM74AS652 Switching Characteristics Symbol Parameter Conditions fMAX Maximum Clock Frequency VCC = 4.5V to 5.5V tPLH Propagation Delay Time R1 = R2 = 500Ω LOW-to-HIGH Level Output CL = 50 pF tPHL From To CBA or CAB Propagation Delay Time A or B Propagation Delay Time tPHL Propagation Delay Time LOW-to-HIGH Level Output SBA or SAB Propagation Delay Time (Note 5) A or B HIGH-to-LOW Level Output tPZH Output Enable Time to HIGH Level Output tPZL Output Enable Time to LOW Level Output tPHZ Enable GBA Output Disable Time Output Disable Time from LOW Level Output tPZH Output Disable Time to HIGH Level Output tPZL Output Disable Time to LOW Level Output tPHZ Enable GAB Output Disable Time Output Disable Time from LOW Level Output Note 5: These parameters are measured with the internal output state of the storage register opposite to that of the bus input. www.fairchildsemi.com 6 ns 2 9 ns 2 9 ns 1 7 ns 2 11 ns 2 9 ns 2 10 ns 3 16 ns 2 9 ns 2 9 ns 3 11 ns 3 16 ns 2 10 ns 2 11 ns B from HIGH Level Output tPLZ 8.5 A from HIGH Level Output tPLZ MHz 2 B or A HIGH-to-LOW Level Output tPLH Units A or B Propagation Delay Time LOW-to-HIGH Level Output tPHL Max 90 HIGH-to-LOW Level Output tPLH Min DM74AS651 • DM74AS652 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 7 www.fairchildsemi.com DM74AS651 • DM74AS652 Octal Bus Transceiver and Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8