DM74LS165N

DM74LS165 8-Bit Parallel In/Serial Output Shift Registers August 1986 Revised March 2000 DM74LS165 8-Bit Parallel In/Serial Output Shift Registers General Description Features This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. ■ Complementary outputs Clocking is accomplished through a 2-input NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking, and holding either clock input LOW with the load input HIGH enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is HIGH. Parallel loading is inhibited as long as the load input is HIGH. Data at the parallel inputs are loaded directly into the register on a HIGH-to-LOW transition of the shift/load input, regardless of the logic levels on the clock, clock inhibit, or serial inputs. ■ Typical power dissipation 105 mW ■ Direct overriding (data) inputs ■ Gated clock inputs ■ Parallel-to-serial data conversion ■ Typical frequency 35 MHz Ordering Code: Order Number Package Number Package Description DM74LS165M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS165WM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Internal Shift/ Clock Clock Serial Parallel Outputs Output A...H QA QB L X X X a...h a b H L L X X H L ↑ H X H QAn QGn H L ↑ L X L QAn QGn H H X X X QA0 QB0 QH0 Load Inhibit QA0 QB0 QH h QH0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively. QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = The level of QA or QG, respectively, before the most recent ↑ transition of the clock. © 2000 Fairchild Semiconductor Corporation DS006399 www.fairchildsemi.com DM74LS165 Logic Diagram Timing Diagram Typical Shift, Load, and Inhibit Sequences www.fairchildsemi.com 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current fCLK Clock Frequency (Note 2) fCLK Clock Frequency (Note 3) tW Pulse Width Clock 25 (Note 3) Load 15 tSU V 2 V 8 mA 0 25 MHz 0 20 MHz Setup Time Parallel 10 (Note 4) Serial 20 Enable 30 Shift 45 tH Hold Time (Note 4) 0 TA Free Air Operating Temperature 0 ns ns ns °C 70 Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V Note 4: TA = 25°C and VCC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL II 2.7 Typ (Note 5) Max Units −1.5 V 3.4 V LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min 0.35 0.5 IOL = 4 mA, VCC = Min 0.25 0.4 Input Current @ Max 0.4 VCC = Max, VI = 7V Input Voltage IIH Min Shift/Load 0.3 Others 0.1 HIGH Level VCC = Max Shift/Load 60 Input Current VI = 2.7V Others 20 LOW Level VCC = Max Shift/Load −1.2 Input Current VI = 0.4V Others −0.4 IOS Short Circuit Output Current VCC = Max (Note 6) ICC Supply Current VCC = Max (Note 7) IIL −20 21 V mA µA mA −100 mA 36 mA Note 5: All typicals are at VCC = 5V, TA = 25° C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: With all outputs OPEN, clock inhibit and shift/load at 4.5V, and a clock pulse applied to the CLOCK input, ICC is measured first with the parallel inputs at 4.5V, then again grounded. 3 www.fairchildsemi.com DM74LS165 Absolute Maximum Ratings(Note 1) DM74LS165 Switching Characteristics at VCC = 5V and TA = 25°C Symbol Parameter fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output www.fairchildsemi.com CL = 15 pF From (Input) To (Output) Min Max 25 RL = 2 kΩ, CL = 50 pF Min Max 20 Units MHz Load to Any Q 35 37 ns Load to Any Q 35 42 ns Clock to Any Q 40 42 ns Clock to Any Q 40 47 ns H to QH 25 27 ns H to QH 30 37 ns H to QH 30 32 ns H to QH 25 32 ns 4 DM74LS165 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16B 5 www.fairchildsemi.com DM74LS165 8-Bit Parallel In/Serial Output Shift Registers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6