DM74LS374N

Revised November 2001 DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description Features These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. ■ Choice of 8 latches or 8 D-type flip-flops in a single package ■ 3-STATE bus-driving outputs ■ Full parallel-access for loading ■ Buffered control inputs ■ P-N-P inputs reduce D-C loading on data lines The eight latches of the DM74LS373 are transparent Dtype latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF. Ordering Code: Order Number Package Number Package Description DM74LS373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide DM74LS373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide DM74LS374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide DM74LS374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation DS006431 www.fairchildsemi.com DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops April 1986 DM74LS373 • DM74LS374 Connection Diagrams DM74LS373 DM74LS374 Function Tables DM74LS373 Output Enable Control G L L DM74LS374 D Output H H H H L L L L X Q0 H X X Z Output Clock D Output L ↑ H H L ↑ L L L L X Q0 H X X Z Control H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don’t Care Z = High Impedance State ↑ = Transition from LOW-to-HIGH level Q0 = The level of the output before steady-state input conditions were established. Logic Diagrams DM74LS373 Transparent Latches www.fairchildsemi.com DM74LS374 Positive-Edge-Triggered Flip-Flops 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V −65°C to +150°C Storage Temperature Range 0°C to +70°C Operating Free Air Temperature Range DM74LS373 Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −2.6 mA IOL LOW Level Output Current 24 mA tW Pulse Width Enable HIGH 15 (Note 3) Enable LOW 15 V 2 tSU Data Setup Time (Note 2) (Note 3) 5↓ tH Data Hold Time (Note 2) (Note 3) 20↓ TA Free Air Operating Temperature 0 V ns ns ns °C 70 Note 2: The symbol (↓) indicates the falling edge of the clock pulse is used for reference. Note 3: TA = 25°C and VCC = 5V. DM74LS373 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Min 2.4 Typ (Note 4) Max Units −1.5 V 3.1 0.35 V 0.5 IOL = 12 mA, VCC = Min 0.4 V II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA 20 µA −20 µA −225 mA 40 mA IOZH IOZL Off-State Output Current with VCC = Max, VO = 2.7V HIGH Level Output Voltage Applied VIH = Min, VIL = Max Off-State Output Current with VCC = Max, VO = 0.4V LOW Level Output Voltage Applied VIH = Min, VIL = Max IOS Short Circuit Output Current VCC = Max (Note 5) ICC Supply Current VCC = Max, OC = 4.5V, −50 Dn, Enable = GND 24 mA Note 4: All typicals are at VCC = 5V, TA = 25°C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. 3 www.fairchildsemi.com DM74LS373 • DM74LS374 Absolute Maximum Ratings(Note 1) DM74LS373 • DM74LS374 DM74LS373 Switching Characteristics at VCC = 5V and TA = 25°C RL = 667Ω Symbol Parameter CL = 45 pF From (Input) To (Output) tPLH Propagation Delay Time ns Data to Q 18 27 ns Enable to Q 30 38 ns Enable to Q 30 36 ns Output Control to Any Q 28 36 ns Output Control to Any Q 36 50 ns Output Control to Any Q 20 ns Output Control to Any Q 25 ns Propagation Delay Time Propagation Delay Time Propagation Delay Time HIGH-to-LOW Level Output tPZH Output Enable Time to HIGH Level Output tPZL Output Enable Time to LOW Level Output tPHZ Output Disable Time from HIGH Level Output (Note 6) tPLZ Output Disable Time from LOW Level Output (Note 6) Units Max 26 LOW-to-HIGH Level Output tPHL CL = 150 pF Min 18 HIGH-to-LOW Level Output tPLH Max Data to Q LOW-to-HIGH Level Output tPHL Min Note 6: CL = 5 pF. DM74LS374 Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −2.6 mA IOL LOW Level Output Current 24 mA tW Pulse Width Clock HIGH 15 (Note 8) Clock LOW 15 2 tSU Data Setup Time (Note 7) (Note 8) 20↑ tH Data Hold Time (Note 7) (Note 8) 1↑ TA Free Air Operating Temperature 0 Note 7: The symbol (↑) indicates the rising edge of the clock pulse is used for reference. Note 8: TA = 25°C and V CC = 5V. www.fairchildsemi.com 4 V V ns ns ns 70 °C over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Min 2.4 IOL = 12 mA, VCC = Min Typ (Note 9) Max Units −1.5 V 3.1 V 0.35 0.5 0.25 0.4 V II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA IOZH Off-State Output Current with VCC = Max, VO = 2.7V HIGH Level Output Voltage Applied VIH = Min, VIL = Max 20 µA Off-State Output Current with VCC = Max, VO = 0.4V LOW Level Output Voltage Applied VIH = Min, VIL = Max −20 µA −225 mA 45 mA IOZL IOS Short Circuit Output Current VCC = Max (Note 10) ICC Supply Current VCC = Max, Dn = GND, OC = 4.5V −50 27 mA Note 9: All typicals are at VCC = 5V, TA = 25°C. Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second. DM74LS374 Switching Characteristics at VCC = 5V and TA = 25°C RL = 667Ω Symbol CL = 45 pF Parameter Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time 35 LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPZH Output Enable Time to HIGH Level Output tPZL Output Enable Time to LOW Level Output tPHZ Output Disable Time from HIGH Level Output (Note 11) tPLZ Max Output Disable Time from LOW Level Output (Note 11) CL = 150 pF Min Units Max 20 MHz 28 32 ns 28 38 ns 28 44 ns 28 44 ns 20 ns 25 ns Note 11: CL = 5 pF. 5 www.fairchildsemi.com DM74LS373 • DM74LS374 DM74LS374 Electrical Characteristics DM74LS373 • DM74LS374 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 6 DM74LS373 • DM74LS374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8