DM74S161N

Revised April 2000 DM74S161 • DM74S163 Synchronous 4-Bit Binary Counters General Description These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. They are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positivegoing) edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a LOW level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable input. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be HIGH to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a HIGH-level output pulse with a duration approximately equal to the HIGH-level portion of the QA output. This HIGH-level overflow ripple carry pulse can be used to enable successive cascaded stages. Features ■ Synchronously programmable ■ Internal look-ahead for fast counting ■ Carry output for n-bit cascading ■ Synchronous counting ■ Load control line ■ Diode-clamped inputs Ordering Code: Order Number Package Number Package Description DM74S161N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74S163N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 Fairchild Semiconductor Corporation DS006471 www.fairchildsemi.com DM74S161 • DM74S163 Synchronous 4-Bit Binary Counters August 1986 DM74S161 • DM74S163 Logic Diagram DM74S161 • DM74S163 www.fairchildsemi.com 2 DM74S161 • DM74S163 Timing Diagram Sequence: 1. Clear outputs to zero 2. Preset to binary twelve 3. Count to thirteen, fourteen, fifteen, zero, one and two 4. Inhibit 3 www.fairchildsemi.com DM74S161 • DM74S163 Parameter Measurement Information Switching Time Waveforms Note A:The input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, ZOUT ≈ 50Ω. For DM74S161/163, t r ≤ 2.5 ns, tf ≤ 2.5 ns. Vary PRR to measure fMAX . Note B: Outputs QDand carry are tested at tn + 16 for DM74S161, SM74S163 where tn is the bit time when all outputs are LOW Note C: VREF = 1.5V. Switching Time Waveforms Note A: The input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, ZOUT ≈ 50Ω. t r ≤ 2.5 ns, tf ≤ 2.5 ns. Vary PRR to measure fMAX. Note B: Enable P and enable T setup times are measured at tn + 0. Note C:VREF = 1.5V. www.fairchildsemi.com 4 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 5.5V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −1 mA IOL LOW Level Output Current 20 mA fCLK Clock Frequency (Note 2) 0 40 Clock Frequency (Note 3) 0 35 tW Pulse Width (Note 2) Pulse Width (Note 3) tSU Setup Time (Note 2) Setup Time (Note 3) tH Hold Time (Note 2) Hold Time (Note 3) 2 Clock 10 Clear (Note 5) 10 Clock 12 Clear (Note 5) 12 Data 4 Enable P or T 12 Load 14 Clear (Note 4) 14 Data 5 Enable P or T 14 Load 16 Clear (Note 4) 16 Data 3 Others 0 Data 5 Others tREL TA V V MHz ns ns ns 2 Load or Clear Release Time (Note 2) 12 Load or Clear Release Time (Note 3) 14 Free Air Operating Temperature 0 ns 70 °C Note 2: CL = 15 pF, RL = 280Ω, TA = 25°C and VCC = 5V. Note 3: CL = 50 pF, RL = 280Ω, TA = 25°C and VCC = 5V. Note 4: Applies only to the DM74S163 which has synchronous clear inputs. Note 5: Applies only to the DM74S161 which has asynchronous clear inputs. 5 www.fairchildsemi.com DM74S161 • DM74S163 Absolute Maximum Ratings(Note 1) DM74S161 • DM74S163 Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIH = Min, VIL = Max Min 2.7 Typ (Note 6) Max Units −1.2 V 3.4 V 0.5 V 1 mA II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V IIH LOW Level VCC = Max CLK, Data Input Current VI = 2.7V Others LOW Level VCC = Max Enable T −4 Input Current VI = 0.5V Others −2 IIL IOS Short Circuit Output Current VCC = Max (Note 7) ICC Supply Current VCC = Max 50 −10 −200 −40 95 µA mA −100 mA 160 mA Note 6: All typicals are at VCC = 5V, TA = 25°C. Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics at VCC = 5V and TA = 25°C RL = 280Ω Symbol Parameter From (Input) To (Output) fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output (Note 8) CL = 15 pF Min Max 40 CL = 50 pF Min 35 MHz Clock to Ripple Carry 25 25 ns Clock to Ripple Carry 25 28 ns Clock to Any Q 15 15 ns Clock to Any Q 15 18 ns Enable T to Ripple Carry 15 18 ns Enable T to Ripple Carry 15 18 ns Clear to Any Q 20 24 ns Note 8: Propagation delay for clearing is measured from clear input for the DM74S161 and from the clock input transition for the DM74S163. www.fairchildsemi.com Units Max 6 DM74S161 • DM74S163 Synchronous 4-Bit Binary Counters Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com