DM74S283N

Revised May 2000 DM74S283 4-Bit Binary Adder with Fast Carry General Description Features These full adders perform the addition of two 4-bit binary numbers. The sum (∑) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial lookahead performance at the economy and reduced package count of a ripple-carry implementation. ■ Full-carry look-ahead across the four bits The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accomplished without the need for logic or level inversion. ■ Typical power dissipation 510 mW ■ Systems achieve partial look-ahead performance with the economy of ripple carry ■ Typical add times Two 8-bit words 15 ns Two 16-bit words 30 ns Ordering Code: Order Number DM74S283N Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 Fairchild Semiconductor Corporation DS006484 www.fairchildsemi.com DM74S283 4-Bit Binary Adder with Fast Carry August 1986 DM74S283 Function Table H = HIGH Level, L = LOW Level Note: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs ∑1 and ∑2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs ∑3, ∑4, and C4. Logic Diagram www.fairchildsemi.com 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 5.5V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max Units 4.75 5 5.25 V VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 IOH HIGH Level Output Current (Output C4) −0.5 2 V TA mA −1 HIGH Level Output Current (Other Outputs) IOL V LOW Level Output Current (Output C4) 10 LOW Level Output Current (Other Outputs) 20 Free Air Operating Temperature 0 mA °C 70 Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIH = Min, VIL = Max Min 2.7 Typ (Note 2) Max Units −1.2 V 3.4 V 0.5 V mA II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 IIH HIGH Level Input Current VCC = Max, VI = 2.7V 50 µA IL LOW Level Input Current VCC = Max, VI = 0.5V −2 mA Short Circuit VCC = Max C4 Output −20 −100 Output Current (Note 3) Other Outputs −40 −100 ICC1 Supply Current VCC = Max (Note 4) 80 120 mA ICC2 Supply Current VCC = Max (Note 5) 95 160 mA IOS mA Note 2: All typicals are at VCC = 5V, TA = 25°C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC1 is measured with all outputs OPEN, all B inputs LOW and all other inputs at 4.5V. Note 5: ICC2 is measured with all outputs OPEN and all inputs at 4.5V. 3 www.fairchildsemi.com DM74S283 Absolute Maximum Ratings(Note 1) DM74S283 Switching Characteristics at VCC = 5V and TA = 25°C RL = 280Ω Symbol Parameter From (Input) To (Output) tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output (Note 6) tPHL Propagation Delay Time HIGH-to-LOW Level Output (Note 6) tPLH Propagation Delay Time LOW-to-HIGH Level Output (Note 6) tPHL Propagation Delay Time HIGH-to-LOW Level Output (Note 6) Min Max CL = 50 pF Min Units Max C0 to ∑1 or ∑2 18 20 ns C0 to ∑1 or ∑2 18 20 ns C0 to ∑3 18 20 ns C0 to ∑3 18 20 ns C0 to ∑4 18 20 ns C0 to ∑4 18 20 ns Ai, Bi to Si 18 20 ns Ai, Bi to Si 18 20 ns C0 to ∑4 11 15 ns C0 to ∑4 11 15 ns Ai, Bi to C4 12 16 ns Ai, Bi to C4 12 16 ns Note 6: RL = 560Ω. www.fairchildsemi.com CL = 15 pF 4 DM74S283 4-Bit Binary Adder with Fast Carry Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com