DM74S374N

Revised May 2000 DM74S373 • DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74S373 are transparent D-type latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74S374 are edge-triggered Dtype flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. Schmitt-trigger buffered inputs at the enable/clock lines simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF. Features ■ Choice of 8 latches or 8 D-type flip-flops in a single package ■ 3-STATE bus-driving outputs ■ Full parallel-access for loading ■ Buffered control inputs ■ P-N-P input reduce D-C loading on data lines Ordering Code: Order Number DM74S373WM Package Number M20B Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74S373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74S374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74S374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams DM74S374N DM74S373N © 2000 Fairchild Semiconductor Corporation DS006486 www.fairchildsemi.com DM74S373 • DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops August 1986 DM74S373 • DM74S374 Truth Tables DM74S373 DM74S374 Output Enable D Control G L H H H L H L L L L X Q0 H X X Z Output Output Clock D Output L ↑ H H L ↑ L L L L X Q0 H X X Z Control H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don’t Care Z = High Impedance State ↑ = Transition from LOW-to-HIGH level, Q0 = The level of the output before steady-state input conditions were established. Logic Diagrams 74S373 Transparent Latches www.fairchildsemi.com 74S374 Positive-Edge-Triggered Flip-Flops 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 5.5V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range DM74S373 Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −6.5 mA IOL LOW Level Output Current 20 mA tW Pulse Width (Note 2) tW V 2 Pulse Width (Note 3) Enable HIGH 6 Enable LOW 7.3 V ns Enable HIGH 15 ns Enable LOW 15 ns ns tSU Data Setup Time (Note 4)(Note 5) 0↓ tH Data Hold Time (Note 4)(Note 5) 10↓ TA Free Air Operating Temperature 0 ns °C 70 Note 2: CL = 15 pF, RL = 280Ω, TA = 25°C and VCC = 5V. Note 3: CL = 50 pF and RL = 280Ω, TA = 25°C and VCC = 5V. Note 4: The symbol (↓) indicates the falling edge of the clock pulse is used for reference. Note 5: TA = 25°C and VCC = 5V. DM74S373 Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIH = Min, VIL = Max Min 2.4 Typ (Note 6) Max Units −1.2 V 3.2 V 0.5 V II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA IIH HIGH Level Input Current VCC = Max, VI = 2.7V 50 µA IIL LOW Level Input Current VCC = Max, VI = 0.5V −250 µA IOZH Off-State Output Current with VCC = Max, VO = 2.4V 50 µA −50 µA HIGH Level Output Voltage Applied VIH = Min, VIL = Max IOZL Off-State Output Current with VCC = Max, VO = 0.5V LOW Level Output Voltage Applied VIH = Min, VIL = Max IOS Short Circuit Output Current VCC = Max (Note 7) ICC Supply Current VCC = Max −40 Outputs HIGH or LOW Outputs Disabled −100 105 160 190 mA mA Note 6: All typicals are at VCC = 5V, TA = 25°C. Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. 3 www.fairchildsemi.com DM74S373 • DM74S374 Absolute Maximum Ratings(Note 1) DM74S373 • DM74S374 DM74S373 Switching Characteristics at VCC = 5V and TA = 25°C RL = 280Ω Symbol Parameter CL = 15 pF From (Input) To (Output) tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPZH Enable Time to HIGH Level Output tPZL Output Enable Time to LOW Level Output tPHZ Output Disable Time to HIGH Level Output (Note 8) tPLZ Output Disable Time to LOW Level Output (Note 8) Min CL = 50 pF Max Min Units Max Data to Any Q 12 14 ns Data to Any Q 12 16 ns Enable to Any Q 14 14 ns Enable to Any Q 18 21 ns Output Control to Any Q 15 17 ns Output Control to Any Q 18 23 ns Output Control to Any Q 9 ns Output Control to Any Q 12 ns Note 8: CL = 5 pF DM74S374 Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VIH HIGH Level Input Voltage Min Nom Max 4.75 5 5.25 Units V V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −6.5 mA IOL LOW Level Output Current fCLK Clock Frequency (Note 9) fCLK Clock Frequency (Note 10) tW Pulse Width Clock HIGH 6 (Note 9) Clock LOW 7.3 Pulse Width Clock HIGH 15 (Note 10) Clock LOW 15 20 mA 0 75 MHz 0 75 MHz tSU Data Setup Time (Note 11)(Note 12) 5↑ tH Data Hold Time (Note 11)(Note 12) 2↑ TA Free Air Operating Temperature 0 Note 9: CL = 15 pF, R L = 280Ω, TA = 25°C and VCC = 5V. Note 10: CL = 50 pF, RL = 280Ω, TA = 25°C and VCC = 5V. Note 11: The symbol (↑) indicates the rising edge of the clock pulse is used for reference. Note 12: TA = 25°C and VCC = 5V. www.fairchildsemi.com 4 ns ns ns 70 °C over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIH = Min, VIL = Max Min 2.4 Typ (Note 13) Max Units −1.2 V 3.2 V 0.5 V II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA IH HIGH Level Input Current VCC = Max, VI = 2.7V 50 µA IIL LOW Level Input Current VCC = Max, VI = 0.5V −250 µA IOZH Off-State Output Current with VCC = Max, VO = 2.4V 50 µA HIGH Level Output Voltage Applied VIH = Min, VIL = Max Off-State Output Current with VCC = Max, VO = 0.5V LOW Level Output Voltage Applied VIH = Min, VIL = Max −50 µA −100 mA IOZL IOS Short Circuit Output Current VCC = Max (Note 14) ICC Supply Current VCC = Max −40 Outputs HIGH 110 Outputs LOW 90 Outputs Disabled 140 mA 160 Note 13: All typicals are at VCC = 5V, TA = 25°C. Note 14: Not more than one output should be shorted at a time, and the duration should not exceed one second. DM74S374 Switching Characteristics at VCC = 5V and TA = 25°C RL = 280Ω Symbol Parameter From (Input) To (Output) fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPZH Output Enable Time to HIGH Level Output tPZL Output Enable Time to LOW Level Output tPHZ Output Disable Time from HIGH Level Output (Note 15) tPLZ Output Disable Time from LOW Level Output (Note 15) CL = 15 pF Min CL = 50 pF Max Min Units Max 75 75 MHz Clock to Any Q 15 15 ns Clock to Any Q 17 20 ns Output Control to Any Q 15 17 ns Output Control to Any Q 18 23 ns Output Control to Any Q 9 ns Output Control to Any Q 12 ns Note 15: CL = 5 pF 5 www.fairchildsemi.com DM74S373 • DM74S374 DM74S374 Electrical Characteristics DM74S373 • DM74S374 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B www.fairchildsemi.com 6 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com DM74S373 • DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Physical Dimensions inches (millimeters) unless otherwise noted (Continued)