ECLTSSOP20EVB
Evaluation Board User's
Manual for High Frequency
TSSOP20
http://onsemi.com
EVAL BOARD USER’S MANUAL
INTRODUCTION
ON Semiconductor has developed an evaluation board for
the devices in 20−lead TSSOP package. These evaluation
boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 20−lead TSSOP device
samples. The board provides a high bandwidth 50 W
controlled impedance environment. Figures 1 and 2 show
the top and bottom view of the evaluation board, which can
be configured in several different ways, depending on
device under test (see Table 1. Configuration List).
This evaluation board manual contains:
•
•
•
•
This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.
Board Lay−Up
The 20−lead TSSOP evaluation board is implemented in
four layers with split (dual) power supplies (see Figure 3.
Evaluation Board Lay−Up). For standard ECL lab setup and
test, a split (dual) power supply is essential to enable the 50
W internal impedance in the oscilloscope as a termination for
ECL devices. The first layer or primary trace layer is 0.008″
thick Rogers RO4003 material, which is designed to have
equal electrical length on all signal traces from the device
under the test (DUT) to the sense output. The second layer
is the 1.0 oz copper ground. The FR4 dielectric material is
placed between second and third layer and between third and
fourth layer. The third layer is the power plane (VCC & VEE)
and a portion of this layer is a ground plane. The fourth layer
is the secondary trace layer.
Information on 20−lead TSSOP Evaluation Board
Assembly Instructions
Appropriate Lab Setup
Bill of Materials
Figure 1. Top View of the 20−lead TSSOP Evaluation Board
© Semiconductor Components Industries, LLC, 2012
January, 2012 − Rev. 2
1
Publication Order Number:
EVBUM2057/D
ECLTSSOP20EVB
Bottom View
Expanded Bottom View
Figure 2. Bottom View of the 20−lead TSSOP Evaluation Board
LAY−UP DETAIL
4 LAYER
SILKSCREEN (TOP SIDE)
LAYER 1 (TOP SIDE) 1 OZ
ROGERS 4003 0.008 in
LAYER 2 (GROUND PLANE P1) 1 OZ
FR−4 0.020 in
LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ
FR−4 0.025 in
LAYER 4 (BOTTOM SIDE) 1 OZ
0.062 $ 0.007
Figure 3. Evaluation Board Lay−up
Board Layout
board. Lists of components and simple schematics are
located in Figures 6 through 12. Place SMA connectors on
J1 through J20, 50 W chip resistors between ground pad and
Pin 1 pad through Pin 20 pad, and chip capacitors C1 through
C5 according to configuration figures. (C4 and C5 are 0.01
mF and C1, C2, and C3 are 0.1ĂmF); (See Figure 5).
The 20−lead TSSOP evaluation board was designed to be
versatile and accommodate several different configurations.
The input, output, and power pin layout of the evaluation
board is shown in Figures 4 and 5. The evaluation board has
at least eight possible configurable options. Table 1, list the
devices and the relevant configuration that utilizes this PCB
http://onsemi.com
2
ECLTSSOP20EVB
Top View
Bottom View
Figure 4. Evaluation Board Layout
http://onsemi.com
3
ECLTSSOP20EVB
VEE
VCC
Pin 20
Pin 1
Ground
Pin 19
Pin 2
Pin 18
Pin 3
Pin 17
Pin 4
Pin 16
Pin 5
Pin 15
Pin 6
Pin 14
Pin 7
Pin 13
Pin 8
Pin 12
Pin 9
Pin 11
Pin 10
C5
C4
Figure 5. Enlarged Bottom View of the Evaluation Board
Table 1. Configuration List
Configuration
Comments
1
See Figure 6
EP14, LVEP14
2
See Figure 7
EP17, LVEP17
3
See Figure 8
EP29
4
See Figure 9
EP40
5
See Figure 10
EP56, LVEP56
6
See Figure 11
EP57
7
See Figure 12
EP139
http://onsemi.com
4
Device
ECLTSSOP20EVB
Evaluation Board Assembly Instructions
The 20−lead TSSOP evaluation board is designed for
characterizing devices in a 50 W laboratory environment
using high bandwidth equipment. Each signal trace on the
board has a via, which has an option of placing a termination
resistor depending on the input/output configuration (see
Table 1, Configuration List). Table 11 contains the Bill of
Materials for this evaluation board.
It is recommended to solder 0.01 mF capacitors to C4 and
C5 to reduce the unwanted noise from the power supplies.
C1, C2, and C3 pads are provided for 0.1 mF capacitor to
further diminish the noise from the power supplies. Adding
capacitors can improve edge rates, reduce overshoot and
undershoot.
Termination
All ECL outputs need to be terminated to VTT (VTT = VCC
–2.0 V = GND) via a 50 W resistor. 0402 chip resistor pads
are provided on the bottom side of the evaluation board to
terminate the ECL driver (More information on termination
is provided in AN8020). Solder the chip resistors to the
bottom side of the board between the appropriate input of the
device pin pads and the ground pads. For ease of assembly,
it is advised to place and solder termination resistors on its
vertical (side) position, instead of its original or flat position.
Solder the Device on the Evaluation Board
The soldering can be accomplished by hand soldering or
soldering re−flow techniques. Make sure pin 1 of the device
is located next to the white dotted mark and all the pins are
aligned to the footprint pads. Solder the 20−lead TSSOP
device to the evaluation board.
Connecting Power and Ground Planes
For standard ECL lab setup and test, a split (dual) power
supply is required enabling the 50 W internal impedance in
the oscilloscope to be used as a termination of the ECL
signals (VTT = VCC – 2.0 V, in split power supply setup, VTT
is the system ground, VCC is 2.0 V, and VEE is –3.0 V or
–1.3 V; see Table 2, Power Supply Levels).
Installing the SMA Connectors
Each configuration indicates the number of SMA
connectors needed to populate an evaluation board for a
given configuration. Each input and output requires one
SMA connector. Attach all the required SMA connectors
onto the board and solder the connectors to the board on J1
through J20. Please note that alignment of the signal
connector pin of the SMA can influence the lab results. The
reflection and launch of the signals are largely influenced by
imperfect alignment and soldering of the SMA connector.
Table 2. Power Supply Levels
Power Supply
VCC
VEE
GND
5.0 V
2.0 V
−3.0 V
0.0 V
3.3 V
2.0 V
−1.3 V
0.0 V
2.5 V
2.0 V
−0.5 V
0.0 V
Validating the Assembled Board
After assembling the evaluation board, it is recommended
to perform continuity checks on all soldered areas before
commencing with the evaluation process. Time Domain
Reflectometry (TDR) is another highly recommended
validation test.
Connect three banana jack sockets to VCC, VEE, and GND
labeled holes. Wire bond the appropriate device pin pad on
the bottom side of the board to VCC and VEE power stripes.
(Device specific, please see configuration for each desired
device. See Figure 5)
http://onsemi.com
5
ECLTSSOP20EVB
CONFIGURATIONS
SMA
CONNECTORS
0603 CHIP
CAPACITOR
0.1 mF
J1
J2
J3
J19
J17
J4
BANANA JACK
PLUG
J5
J16
J6
J7
J14
J8
J13
J12
J9
J10
NORMAL TOP VIEW
EP14 / LVEP14
0603 CHIP
CAPACITOR
0.01 mF
PIN 1
VEE
VCC
WIRE
0402 CHIP
RESISTOR
50 W
0805 CHIP
CAPACITOR
0.01 mF
EXPANDED BOTTOM VIEW
EP14 / LVEP14
Figure 6. Configuration 1
Table 3. Configuration 1 (Device EP14 and LVEP14)
Device
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Connector
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Resistor
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
No
Yes
Yes
No
Yes
No
Power
No
No
No
No
No
No
No
No
No
No
VEE
No
No
No
No
No
No
VCC
No
VCC
http://onsemi.com
6
ECLTSSOP20EVB
SMA
CONNECTORS
0603 CHIP
CAPACITOR
0.1 mF
J2
J3
J19
J18
J17
J4
BANANA JACK
PLUG
J5
J16
J6
J15
J7
J14
J8
J13
J12
J9
NORMAL TOP VIEW
EP17 / LVEP17
0603 CHIP
CAPACITOR
0.01 mF
PIN 1
VEE
VCC
0402 CHIP
RESISTOR
50 W
WIRE
0805 CHIP
CAPACITOR
0.01 mF
EXPANDED BOTTOM VIEW
EP17 / LVEP17
Figure 7. Configuration 2
Table 4. Configuration 2 (Device EP17 and LVEP17)
Device
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Connector
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Resistor
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
Power
VCC
No
No
No
No
No
No
No
No
No
VEE
No
No
No
No
No
No
No
No
VCC
http://onsemi.com
7
ECLTSSOP20EVB
SMA
CONNECTORS
0603 CHIP
CAPACITOR
0.1 mF
J1
J2
J3
J19
J18
J17
J4
BANANA JACK
PLUG
J5
J16
J6
J15
J7
J14
J8
J13
J12
J9
NORMAL TOP VIEW
EP29
0603 CHIP
CAPACITOR
0.01 mF
PIN 1
VEE
VCC
0402 CHIP
RESISTOR
50 W
WIRE
0805 CHIP
CAPACITOR
0.01 mF
EXPANDED BOTTOM VIEW
EP29
Figure 8. Configuration 3
Table 5. Configuration 3 (Device EP29)
Device
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Connector
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Resistor
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
No
No
Yes
Yes
No
Power
No
No
No
No
No
No
No
No
No
VCC
VEE
No
No
No
No
No
No
No
No
VCC
http://onsemi.com
8
ECLTSSOP20EVB
SMA
CONNECTORS
0603 CHIP
CAPACITOR
0.1 mF
J2
J3
J19
J17
J4
BANANA JACK
PLUG
J5
J16
J6
J15
J7
J14
J8
J9
J10
0603 CHIP
CAPACITOR
0.01 mF
PIN 1
0603 CHIP
CAPACITOR
0.01 mF
NORMAL TOP VIEW
EP40
VEE
VEE
VCC
VCC
WIRE
PIN 1
0402 CHIP
RESISTOR
50 W
WIRE
0805 CHIP
CAPACITOR EXPANDED BOTTOM VIEW
EP40
0.01 mF
(Option 1 Internal Termination Resistor)
0805 CHIP
CAPACITOR EXPANDED BOTTOM VIEW
EP40
0.01 mF
(Option 2 External Termination Resistor)
Figure 9. Configuration 4
Table 6. Configuration 4 (Device EP40) (Options 1 & 2)
Device
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Option 1 Internal Termination Resistor Configuration
Connector
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Yes
No
Yes
No
Resistor
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Power
VEE
Gnd
Gnd
No
No
No
No
Gnd
Gnd
No
VEE
No
VCC
No
No
No
No
VCC
No
VCC
No
No
No
Yes
Yes
Yes
Yes
No
Yes
No
Option 2 External Termination Resistor Configuration
Connector
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Resistor
No
No
No
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
Power
VEE
No
No
No
No
No
No
No
No
No
VEE
No
VCC
No
No
No
No
VCC
No
VCC
http://onsemi.com
9
ECLTSSOP20EVB
SMA
CONNECTORS
0603 CHIP
CAPACITOR
0.1 mF
J1
J2
J19
J18
J17
J4
BANANA JACK
PLUG
J5
J16
J6
J15
J7
J13
J12
J9
J10
NORMAL TOP VIEW
EP56 / LVEP56
PIN 1
VEE
VCC
0603 CHIP
CAPACITOR
0.01 mF
0402 CHIP
RESISTOR
50 W
WIRE
0805 CHIP
CAPACITOR
0.01 mF
EXPANDED BOTTOM VIEW
EP56 / LVEP56
Figure 10. Configuration 5
Table 7. Configuration 5 (Device EP56 and LVEP56)
Device
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Connector
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
No
Resistor
Yes
Yes
No
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
Yes
Yes
Yes
No
No
No
Power
No
No
No
No
No
No
No
No
No
No
VEE
No
No
VCC
No
No
No
No
No
VCC
http://onsemi.com
10
ECLTSSOP20EVB
SMA
CONNECTORS
0603 CHIP
CAPACITOR
0.1 mF
J2
J3
J19
J18
J4
BANANA JACK
PLUG
J5
J16
J6
J15
J7
J8
J13
J12
J9
NORMAL TOP VIEW
EP57
PIN 1
VEE
VCC
0603 CHIP
CAPACITOR
0.01 mF
0402 CHIP
RESISTOR
50 W
WIRE
0805 CHIP
CAPACITOR
0.01 mF
EXPANDED BOTTOM VIEW
EP57
Figure 11. Configuration 6
Table 8. Configuration 6 (Device EP57)
Device
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Connector
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Resistor
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Yes
Yes
No
Power
VCC
No
No
No
No
No
No
No
No
VEE
VEE
No
No
VCC
No
No
VCC
No
No
VCC
http://onsemi.com
11
ECLTSSOP20EVB
SMA
CONNECTORS
0603 CHIP
CAPACITOR
0.1 mF
J2
J3
J19
J18
J17
J4
BANANA JACK
PLUG
J5
J16
J6
J15
J7
J14
J13
J12
J9
J10
NORMAL TOP VIEW
EP139
0603 CHIP
CAPACITOR
0.01 mF
PIN 1
VEE
VCC
WIRE
0402 CHIP
RESISTOR
50 W
0805 CHIP
CAPACITOR
0.01 mF
EXPANDED BOTTOM VIEW
EP139
Figure 12. Configuration 7
Table 9. Configuration 7 (Device EP139)
Device
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
No
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Resistor
No
Yes
Yes
Yes
Yes
No
Yes
No
Yes
Yes
No
No
No
No
No
No
No
No
No
No
Power
VCC
No
No
No
No
No
No
VCC
No
No
VEE
No
No
No
No
No
No
No
No
VCC
Connector
http://onsemi.com
12
ECLTSSOP20EVB
LAB SETUP
Power Supply
VCC GND
VEE
Test
Measuring
Equipment
Channel 1
J1
J2
Channel 2
Channel 3
J3
Channel 4
J4
Channel 5
J5
Channel 6
Channel 7
Differential
Signal
Generator
D
U
T
J13
Out1
J12
Out1
J6
J7
J8
Channel 8
Trigger
Trigger
Figure 13. Example of Standard Lab Setup (Configuration 1)
1. Connect appropriate power supplies to VCC, VEE,
and GND.
For standard ECL lab setup and test, a split (dual)
power supply is required enabling the 50 W
internal impedance in the oscilloscope to be used
as a termination of the ECL signals (VTT = VCC
– 2.0 V, in split power supply setup, VTT is the
system ground, VCC is 2.0 V, and VEE is –3.0 V or
–1.3 V; see Table 10).
2. Connect a signal generator to the input SMA
connectors. Setup input signal according to the
device data sheet.
3. Connect a test measurement device on the device
output SMA connectors.
NOTE: The test measurement device must contain 50 W
termination.
Table 10. Power Supply Levels
Power Supply
VCC
VEE
GND
5.0 V
2.0 V
−3.0 V
0.0 V
3.3 V
2.0 V
−1.3 V
0.0 V
2.5 V
2.0 V
−0.5 V
0.0 V
http://onsemi.com
13
ECLTSSOP20EVB
Table 11. Bill of Materials
Components
Manufacturer
Description
SMA Connector
Johnson
Components*
SMA Connector, Side
Launch, Gold Plated
Banana Jack
Chip Capacitor
Chip Resistor
Keystone*
Johanson
Dielectric*
Panasonic*
Part Number
142−0701−851
Web Site
http://www.johnsoncomponents.com
http://www.keyelco.com
Standard Jack
6096
Miniature Jack
6090
0603 0.01 mF
500R14Z100MV4E
0805 0.01 mF
500R15Z100MV4E
0603 0.1 mF
250R14Z101MV4E
0402 50 W ± 1% Precision
Think Film Chip Resistor
ERJ−2RKF49R9X
http://www.panasonic.com
http://www.johansondielectrics.com
Evaluation Board
ON Semiconductor
TSSOP 20 Evaluation Board
ECLTSSOP20EVB
http://www.onsemi.com
Device Samples
ON Semiconductor
TSSOP 20 Package Device
Various
http://www.onsemi.com
*Components are available through most distributors, i.e. www.newark.com, www.digikey.com.
http://onsemi.com
14
ECLTSSOP20EVB
Top View
Second Layer (Ground Plane)
Figure 14. Gerber Files
http://onsemi.com
15
ECLTSSOP20EVB
Third Layer (Power and Ground Plane)
(Left side − VCC, Right side − VEE, Middle Box − Ground)
Bottom Layer
Figure 15. Gerber Files
http://onsemi.com
16
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A
listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
The evaluation board/kit (research and development board/kit) (hereinafter the “board”) is not a finished product and is not available for sale to consumers. The board is only intended
for research, development, demonstration and evaluation purposes and will only be used in laboratory/development areas by persons with an engineering/technical training and familiar
with the risks associated with handling electrical/mechanical components, systems and subsystems. This person assumes full responsibility/liability for proper and safe handling. Any
other use, resale or redistribution for any other purpose is strictly prohibited.
THE BOARD IS PROVIDED BY ONSEMI TO YOU “AS IS” AND WITHOUT ANY REPRESENTATIONS OR WARRANTIES WHATSOEVER. WITHOUT LIMITING THE FOREGOING,
ONSEMI (AND ITS LICENSORS/SUPPLIERS) HEREBY DISCLAIMS ANY AND ALL REPRESENTATIONS AND WARRANTIES IN RELATION TO THE BOARD, ANY
MODIFICATIONS, OR THIS AGREEMENT, WHETHER EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, INCLUDING WITHOUT LIMITATION ANY AND ALL
REPRESENTATIONS AND WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, NON−INFRINGEMENT, AND THOSE ARISING FROM A
COURSE OF DEALING, TRADE USAGE, TRADE CUSTOM OR TRADE PRACTICE.
onsemi reserves the right to make changes without further notice to any board.
You are responsible for determining whether the board will be suitable for your intended use or application or will achieve your intended results. Prior to using or distributing any systems
that have been evaluated, designed or tested using the board, you agree to test and validate your design to confirm the functionality for your application. Any technical, applications or
design information or advice, quality characterization, reliability data or other services provided by onsemi shall not constitute any representation or warranty by onsemi, and no additional
obligations or liabilities shall arise from onsemi having provided such information or services.
onsemi products including the boards are not designed, intended, or authorized for use in life support systems, or any FDA Class 3 medical devices or medical devices with a similar
or equivalent classification in a foreign jurisdiction, or any devices intended for implantation in the human body. You agree to indemnify, defend and hold harmless onsemi, its directors,
officers, employees, representatives, agents, subsidiaries, affiliates, distributors, and assigns, against any and all liabilities, losses, costs, damages, judgments, and expenses, arising
out of any claim, demand, investigation, lawsuit, regulatory action or cause of action arising out of or associated with any unauthorized use, even if such claim alleges that onsemi was
negligent regarding the design or manufacture of any products and/or the board.
This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC,
CE or UL, and may not meet the technical requirements of these or other related directives.
FCC WARNING – This evaluation board/kit is intended for use for engineering development, demonstration, or evaluation purposes only and is not considered by onsemi to be a finished
end product fit for general consumer use. It may generate, use, or radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant
to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment may cause interference with radio
communications, in which case the user shall be responsible, at its expense, to take whatever measures may be required to correct this interference.
onsemi does not convey any license under its patent rights nor the rights of others.
LIMITATIONS OF LIABILITY: onsemi shall not be liable for any special, consequential, incidental, indirect or punitive damages, including, but not limited to the costs of requalification,
delay, loss of profits or goodwill, arising out of or in connection with the board, even if onsemi is advised of the possibility of such damages. In no event shall onsemi’s aggregate liability
from any obligation arising out of or in connection with the board, under any theory of liability, exceed the purchase price paid for the board, if any.
The board is provided to you subject to the license and other terms per onsemi’s standard terms and conditions of sale. For more information and documentation, please visit
www.onsemi.com.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
www.onsemi.com
1
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
