ESD5481MUT5G

ESD5481 ESD Protection Diode Micro−Packaged Diodes for ESD Protection The ESD5481 is designed to protect voltage sensitive components from ESD. Excellent clamping capability, low leakage, and fast response time provide best in class protection on designs that are exposed to ESD. Because of its small size, it is suited for use in cellular phones, MP3 players, digital cameras and many other portable applications where board space comes at a premium. www.onsemi.com 1 Specification Features • • • • • • • • • • Low Capacitance 15 pF Low Clamping Voltage Small Body Outline Dimensions: 0.60 mm x 0.30 mm Low Body Height: 0.3 mm Stand−off Voltage: 5.0 V Low Leakage Response Time is < 1 ns IEC61000−4−2 Level 4 ESD Protection IEC61000−4−4 Level 4 EFT Protection These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant X3DFN2 CASE 152AF AM A = Specific Device Code M = Date Code ORDERING INFORMATION Package Shipping† X3DFN2 (Pb−Free) 10,000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MAXIMUM RATINGS Symbol Value Unit IEC 61000−4−2 (ESD) Contact Air ±20 ±20 kV IEC 61000−4−4 (EFT) 5/50 ns 40 A Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Thermal Resistance, Junction−to−Ambient °PD° 300 mW RqJA 400 °C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C TL 260 °C Lead Solder Temperature − Maximum (10 Second Duration) PIN 1 ESD5481MUT5G Device Meets MSL 1 Requirements Rating MARKING DIAGRAM Device Mechanical Characteristics MOUNTING POSITION: Any QUALIFIED MAX REFLOW TEMPERATURE: 260°C 2 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2016 September, 2017 − Rev. 9 1 Publication Order Number: ESD5481/D ESD5481 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) IPP Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR IT IR VRWM VBR VC IT Working Peak Reverse Voltage V RDYN Breakdown Voltage @ IT IPP Test Current RDYN RDYN IT VC VBR VRWM IR Maximum Reverse Leakage Current @ VRWM VBR I Dynamic Resistance Bi−Directional *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Reverse Working Voltage Symbol VRWM Conditions Min Typ I/O Pin to I/O Pin Max Unit 5.0 V Breakdown Voltage VBR IT = 5 mA 4.5 10 V Breakdown Voltage VBR IT = 1 mA 5.7 8.0 V 1.0 mA Reverse Leakage Current IR VRWM = 5.0 V Clamping Voltage (Note 2) VC IEC61000−4−2, ±8 kV Contact Clamping Voltage TLP (Note 3) VC IPP = 16 A IPP = −16 A Clamping Voltage 8/20 ms Waveform per Figure 10 VC Dynamic Resistance RDYN See Figures 1 and 2 V 19.7 −11 23 −13 V IPP = 1 A IPP = 2 A 9.8 12.4 12 15 V Pin 1 to Pin 2 Pin 2 to Pin 1 0.49 0.28 W A IEC 61000−4−2 Level 2 equivalent (±8 kV Contact, ±15 kV Air) Reverse Peak Pulse Current IPP per IEC 61000−4−5 (8/20 ms) Figure 10 2.0 Junction Capacitance CJ VR = 0 V, f = 1 MHz 12 15 pF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. For test procedure see application note AND8307/D. 3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 www.onsemi.com 2 ESD5481 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec Oscilloscope ESD Gun 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger www.onsemi.com 3 ESD5481 −24 20 −22 10 12 6 10 4 8 6 4 0 2 4 6 8 10 12 14 16 18 20 22 24 TLP Current[A] 14 EQUIVALENT VIEC (kV) 8 16 2 0 12 10 −20 18 TLP Current [A] −26 12 22 −18 8 −16 −14 6 −12 −10 4 −8 −6 2 −4 0 −2 0 2 0 −2 −4 −6 Vc [V] Figure 5. Positive TLP I−V Curve NOTE: EQUIVALENT VIEC (kV) 24 −8 Vc [V] −10 −12 −14 0 Figure 6. Negative TLP I−V Curve TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description below for more information. Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 7. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 8 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. For more information on TLP measurements and how to interpret them please refer to AND9007/D. S Attenuator ÷ 50 W Coax Cable 10 MW IM 50 W Coax Cable VM DUT VC Oscilloscope Figure 7. Simplified Schematic of a Typical TLP System www.onsemi.com 4 ESD5481 Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms 1E−02 1E−03 1E−04 1E−05 1E−06 1E−08 1E−09 1E−10 1E−11 1E−12 1E−13 1E−14 −8 −6 −4 −2 0 V1[V] 2 4 6 8 Figure 9. IV Characteristics 100 % OF PEAK PULSE CURRENT I [A] 1E−07 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 10. 8 X 20 ms Pulse Waveform www.onsemi.com 5 80 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS X3DFN2, 0.62x0.32, 0.355P, (0201) CASE 152AF ISSUE A DATE 17 FEB 2015 SCALE 8:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. A B D PIN 1 INDICATOR (OPTIONAL) DIM A A1 b D E e L2 E TOP VIEW 0.05 C A 2X 0.05 C A1 SIDE VIEW C MILLIMETERS MIN MAX 0.25 0.33 −−− 0.05 0.22 0.28 0.58 0.66 0.28 0.36 0.355 BSC 0.17 0.23 GENERIC MARKING DIAGRAM* SEATING PLANE PIN 1 XM e 1 2X 0.05 M 2 2X b X = Specific Device Code M = Date Code 0.05 L2 M C A B RECOMMENDED MOUNTING FOOTPRINT* C A B BOTTOM VIEW 0.74 2X 0.30 1 2X 0.31 DIMENSIONS: MILLIMETERS See Application Note AND8398/D for more mounting details *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON56472E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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