ESD7102BT1G

ESD7102, SZESD7102 ESD Protection Diodes Low Capacitance ESD Protection Diodes for High Speed Data Line The ESD7102 transient voltage suppressor is designed to protect high speed data lines from ESD. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The small form factor, flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as USB 3.0 and HDMI. Features • MARKING DIAGRAM 3 1 • Low Capacitance (0.3 pF Typical, I/O to GND) • Short to Battery Survivability • Protection for the Following IEC Standards: • • www.onsemi.com SC−75 CASE 463 2 1 E5 M IEC 61000−4−2 Level 4 (ESD) Low ESD Clamping Voltage (34 V Typical, +8 A TLP, I/O to GND) SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant E5 M = Specific Device Code = Date Code PIN CONFIGURATION AND SCHEMATIC Pin 1 Pin 2 Typical Applications • • • • USB2.0/3.0 LVDS HDMI High Speed Differential Pairs Pin 3 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range TJ −55 to +150 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C IEC 61000−4−2 Contact IEC 61000−4−2 Air ISO 10605 Contact (330 pF / 330 W) ISO 10605 Contact (330 pF / 2 kW) ISO 10605 Contact (150 pF / 2 kW) ESD ±8 ±15 ±8 ±20 ±27 kV = ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. © Semiconductor Components Industries, LLC, 2015 October, 2017 − Rev. 1 1 Publication Order Number: ESD7102/D ESD7102, SZESD7102 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Conditions VRWM I/O Pin to GND Reverse Working Voltage Breakdown Voltage Min Typ Max Unit 16 V 1 mA VBR IT = 1 mA, I/O Pin to GND Reverse Leakage Current IR VRWM = 5 V, I/O Pin to GND 16.5 V Clamping Voltage (Note 1) VC IEC61000−4−2, ±8 kV Contact See Figures 1 and 2 Clamping Voltage TLP (Note 2) VC IPP = 8 A IPP = 16 A IPP = −8 A IPP = −16 A 34 55 −5.3 −10 V W Dynamic Resistance (Note 2) IR TLP Pulse 1.5 Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins VR = 0 V, f = 1 MHz between I/O Pins and GND 0.2 0.3 0.4 0.5 pF DCJ VR = 0 V, f = 1 MHz between I/O1 to GND and I/O 2 to GND 5 10 % f = 1 GHz f = 3 GHz 0.1 0.2 dB RL = 50 W 5 GHz Junction Capacitance Match Insertion Loss 3dB Bandwidth fBW 120 20 100 0 80 −20 VOLTAGE (V) VOLTAGE (V) 1. For test procedure see Figures 5 and 6 and application note AND8307/D. 2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. 60 40 20 0 −40 −60 −80 −100 −20 −25 25 0 50 75 100 TIME (ns) 125 150 175 −120 −25 Figure 1. IEC61000−4−2 +8 kV Contact ESD Clamping Voltage 0.45 1E−04 0.40 CAPACITANCE (pF) 0.50 1E−03 CURRENT (A) 1E−05 1E−06 1E−07 1E−08 1E−09 8 10 12 150 175 0.20 0.15 0.05 6 125 0.25 0.10 4 75 100 TIME (ns) 0.30 1E−11 2 50 0.35 1E−10 0 25 Figure 2. IEC61000−4−2 −8 kV Contact ESD Clamping Voltage 1E−02 1E−12 −2 0 14 16 18 20 22 24 0 0 VOLTAGE (V) 2 4 6 8 10 12 14 BIAS VOLTAGE (V) Figure 3. Typical IV Characteristic Curve Figure 4. Typical CV Characteristic Curve www.onsemi.com 2 16 ESD7102, SZESD7102 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 5. IEC61000−4−2 Spec ESD Gun Oscilloscope DUT 50 W Cable 50 W Figure 6. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger www.onsemi.com 3 ESD7102, SZESD7102 20 10 18 8 8 −16 EQUIVALENT VIEC (kV) TLP CURRENT (A) TLP CURRENT (A) 16 −14 12 6 10 6 −12 −10 8 4 6 4 2 4 −8 −6 −4 2 −2 2 10 20 30 40 50 0 0 0 60 −2 −4 −6 −10 −8 VOLTAGE (V) VOLTAGE (V) Figure 7. Positive TLP IV Curve Figure 8. Negative TLP IV Curve Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 9. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 10 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. 50 W Coax Cable S Attenuator ÷ 50 W Coax Cable 10 MW IM 0 −12 VM DUT VC Oscilloscope Figure 9. Simplified Schematic of a Typical TLP System Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 4 EQUIVALENT VIEC (kV) −18 14 0 0 10 −20 ESD7102, SZESD7102 Without ESD7102 With ESD7102 Figure 11. USB3.0 Eye Diagram with and without ESD7102 at 5 Gb/s 1 0.50 0 0.45 −1 0.40 CAPACITANCE (pF) −2 S21 (dB) −3 −4 −5 −6 −7 0.35 0.30 0.25 0.20 0.15 −8 0.10 −9 0.05 −10 1.E+07 1.E+08 1.E+09 FREQUENCY (Hz) 0.0 0.0E+00 1.E+10 VR = 0 V 1.0E+09 2.0E+09 3.0E+09 FREQUENCY (Hz) Figure 12. Typical Insertion Loss Figure 13. Typical Capacitance over Frequency ORDERING INFORMATION Package Shipping† ESD7102BT1G SC−75 (Pb−Free) 3000 / Tape & Reel SZESD7102BT1G* SC−75 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−75/SOT−416 CASE 463−01 ISSUE G 3 1 2 DATE 07 AUG 2015 SCALE 4:1 −E− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 2 3 b 3 PL 0.20 (0.008) e DIM A A1 b C D E e L HE −D− 1 M D HE C 0.20 (0.008) E A L MILLIMETERS MIN NOM MAX 0.70 0.80 0.90 0.00 0.05 0.10 0.15 0.20 0.30 0.10 0.15 0.25 1.55 1.60 1.65 0.70 0.80 0.90 1.00 BSC 0.10 0.15 0.20 1.50 1.60 1.70 INCHES NOM MAX 0.031 0.035 0.002 0.004 0.008 0.012 0.006 0.010 0.063 0.065 0.031 0.035 0.04 BSC 0.004 0.006 0.008 0.060 0.063 0.067 MIN 0.027 0.000 0.006 0.004 0.061 0.027 GENERIC MARKING DIAGRAM* A1 STYLE 1: PIN 1. BASE 2. EMITTER 3. COLLECTOR STYLE 2: PIN 1. ANODE 2. N/C 3. CATHODE STYLE 4: PIN 1. CATHODE 2. CATHODE 3. ANODE STYLE 5: PIN 1. GATE 2. SOURCE 3. DRAIN XX M G STYLE 3: PIN 1. ANODE 2. ANODE 3. CATHODE 1 XX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. SOLDERING FOOTPRINT* 0.356 0.014 1.803 0.071 0.508 0.020 0.787 0.031 1.000 0.039 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB15184C SC−75/SOT−416 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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