ESD7C, SZESD7C SERIES
ESD Protection Diode
Micro−Packaged Diodes for ESD Protection
The ESD7CxxD Series is designed to protect voltage sensitive
components from ESD. Excellent clamping capability, low leakage, and
fast response time make these parts ideal for ESD protection on designs
where board space is at a premium. Because of its small size, it is suited
for use in cellular phones, portable devices, digital cameras, power
supplies and many other portable applications.
Specification Features:
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PIN 1. CATHODE
2. CATHODE
3. ANODE
1
3
2
• Low Capacitance 6.2 pF to 13 pF
• Low Clamping Voltage
• Small Body Outline Dimensions:
•
•
•
•
•
•
•
•
0.047″ x 0.047″ (1.20 mm x 1.20 mm)
Low Body Height: 0.020″ (0.5 mm)
Stand−off Voltage: 3.3 V, 5 V
Low Leakage
Response Time < 1 ns
ESD Rating of Class 3 (> 16 kV) per Human Body Model
IEC61000−4−2 Level 4 ESD Protection
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These are Pb−Free Devices
Mechanical Characteristics:
CASE: Void-free, transfer-molded, thermosetting plastic
MARKING
DIAGRAM
L5 M
SOT−723
CASE 631AA
L5
M
*Date Code orientation and/or position may
vary depending upon manufacturing location.
ORDERING INFORMATION
Package
Shipping†
ESD7CxxDT5G
SOT−723
(Pb−Free)
8000 /
Tape & Reel
SZESD7CxxDT5G
SOT−723
(Pb−Free)
8000 /
Tape & Reel
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
Device Meets MSL 1 Requirements
MAXIMUM RATINGS
IEC 61000−4−2 (ESD)
Symbol
Contact
Air
Total Power Dissipation on FR−5 Board
(Note 1) @ TA = 25°C
Derate above 25°C
Thermal Resistance Junction−to−Ambient
RqJA
Junction and Storage Temperature Range
Lead Solder Temperature − Maximum
(10 Second Duration)
⎪
PD
= Specific Device Code
= Date Code
Device
Epoxy Meets UL 94 V−0
LEAD FINISH: 100% Matte Sn (Tin)
MOUNTING POSITION: Any
Rating
1
Value
Unit
±8.0
±15
kV
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
DEVICE MARKING INFORMATION
240
1.9
525
mW
mW/°C
°C/W
TJ, Tstg
−55 to
+150
°C
TL
260
°C
See specific marking information in the device marking
column of the table on page 2 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2012
November, 2017 − Rev. 4
1
Publication Order Number:
ESD7C3.3D/D
ESD7C, SZESD7C SERIES
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
IF
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
Working Peak Reverse Voltage
Test Current
IF
Forward Current
VF
Forward Voltage @ IF
Ppk
Peak Power Dissipation
V
IR VF
IT
Breakdown Voltage @ IT
IT
C
VC VBR VRWM
Maximum Reverse Leakage Current @ VRWM
IPP
Max. Capacitance @VR = 0 and f = 1 MHz
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Uni−Directional
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 1.1 V Max. @ IF = 10 mA)
VRWM (V)
IR (mA) @ VRWM
VBR (V) @ IT
(Note 3)
IT
C (pF)
(Note 4)
C (pF)
(Note 4)
VC
Per IEC61000−4−2
(Note 5)
Device (Note 2)
Device
Marking
Max
Max
Min
mA
Typ
Max
ESD7C3.3DT5G
L5
3.3
1.0
5.0
1.0
12
13
ESD7C5.0DT5G
L4
5.0
0.5
11
1.0
6.0
6.2
2.
3.
4.
5.
6.
Figures 1 and 2
See Below
(Note 6)
Include SZ−prefix devices where applicable.
VBR is measured with a pulse test current IT at an ambient temperature of 25°C.
Capacitance of one diode at f = 1 MHz, VR = 0 V, TA = 25°C.
For test procedure see Figures 3 and 4 and Application Note AND8307/D.
ESD7C5.0DT5G shown below. Other voltages available upon request.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
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2
ESD7C, SZESD7C SERIES
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test
Voltage
(kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Device
ESD Gun
Under
Oscilloscope
Test
50 W
50 W
Cable
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−723
CASE 631AA−01
ISSUE D
DATE 10 AUG 2009
SCALE 4:1
−X−
D
b1
A
−Y−
3
E
1
2X
HE
2
2X
e
b
C
0.08 X Y
3X
1
3X
DIM
A
b
b1
C
D
E
e
HE
L
L2
SIDE VIEW
TOP VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
L
GENERIC
MARKING DIAGRAM*
L2
BOTTOM VIEW
STYLE 1:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. N/C
3. CATHODE
STYLE 3:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. ANODE
STYLE 5:
PIN 1. GATE
2. SOURCE
3. DRAIN
XX M
1
XX
M
RECOMMENDED
SOLDERING FOOTPRINT*
= Specific Device Code
= Date Code
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
2X
0.40
2X
MILLIMETERS
MIN
NOM
MAX
0.45
0.50
0.55
0.15
0.21
0.27
0.25
0.31
0.37
0.07
0.12
0.17
1.15
1.20
1.25
0.75
0.80
0.85
0.40 BSC
1.15
1.20
1.25
0.29 REF
0.15
0.20
0.25
0.27
PACKAGE
OUTLINE
1.50
3X
0.52
0.36
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12989D
SOT−723
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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