ESD8104MUTAG

ESD8104 ESD Protection Diode Low Capacitance Array for High Speed Data Lines The ESD8104 is designed to protect high speed data lines from ESD. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as USB 3.0/3.1 and HDMI 2.0. Features • Low Capacitance (0.37 pF Max, I/O to GND) • Protection for the Following IEC Standards: IEC 61000−4−2 (Level 4) • Low ESD Clamping Voltage • SZ Prefix for Automotive and Other Applications Requiring Unique • Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • • • • USB 3.0/3.1 eSATA HDMI 1.3/1.4/2.0 DisplayPort www.onsemi.com MARKING DIAGRAM UDFN10 CASE 517BB 4C MG G 4C = Specific Device Code (tbd) M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PIN CONFIGURATION AND SCHEMATIC N/C N/C GND N/C N/C 10 9 8 7 6 1 2 3 4 5 I/O I/O GND I/O I/O I/O Pin 1 I/O Pin 2 I/O Pin 4 I/O Pin 5 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range TJ −55 to +125 °C Storage Temperature Range Tstg −55 to +150 °C TL 260 °C ESD ESD ±15 ±15 kV kV Lead Solder Temperature − Maximum (10 Seconds) IEC 61000−4−2 Contact (ESD) IEC 61000−4−2 Air (ESD) Pins 3, 8 Note: Common GND − Only Minimum of 1 GND connection required = Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ORDERING INFORMATION Device See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2015 November, 2017 − Rev. 8 Package Shipping ESD8104MUTAG UDFN10 (Pb−Free) 3000 / Tape & Reel SZESD8104MUTAG UDFN10 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 Publication Order Number: ESD8104/D ESD8104 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) Symbol IPP Parameter IPP Maximum Peak Pulse Current VC Clamping Voltage @ IPP VRWM RDYN Working Peak Reverse Voltage IR VCL VBR VRWM VBR Breakdown Voltage @ IT IT VCL RDYN Test Current RDYN V IR IT Maximum Reverse Leakage Current @ VRWM Dynamic Resistance *See Application Note AND8308/D for detailed explanations of datasheet parameters. IPP Uni−Directional ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage VRWM Breakdown Voltage VBR Conditions IT = 1 mA, I/O Pin to GND IR VRWM = 3.3 V, I/O Pin to GND Clamping Voltage (Note 1) VC IEC61000−4−2, ±8 kV Contact Clamping Voltage TLP (Note 2) See Figures 5 through 8 VC IPP = 8 A IPP = −8 A IPP = 16 A IPP = −16 A RDYN Junction Capacitance CJ Typ 4.0 5.0 Max Unit 3.3 V I/O Pin to GND Reverse Leakage Current Dynamic Resistance Min V 1.0 mA See Figures 1 and 2 V IEC 61000−4−2 Level 2 equivalent (±4 kV Contact, ±4 kV Air) 8.5 −4.5 V IEC 61000−4−2 Level 4 equivalent (±8 kV Contact, ±15 kV Air) 11.4 −8.0 I/O Pin to GND GND to I/O Pin 0.36 0.44 VR = 0 V, f = 1 MHz between I/O Pins and GND VR = 0 V, f = 1 MHz between I/O Pins VR = 0 V, f = 1 MHz, TA = 65°C between I/O Pins and GND 0.30 0.15 0.37 W 0.37 0.20 0.47 pF 1. For test procedure see Figures 3 and 4 and application note AND8307/D. 2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. 10 80 0 70 −10 60 −20 VOLTAGE (V) VOLTAGE (V) 90 50 40 30 20 −30 −40 −50 −60 10 −70 0 −80 −10 −20 0 20 40 60 80 100 120 −90 −20 140 0 20 40 60 80 100 120 TIME (ns) TIME (ns) Figure 1. IEC61000−4−2 +8 kV Contact Clamping Voltage Figure 2. IEC61000−4−2 −8 kV Contact Clamping Voltage www.onsemi.com 2 140 ESD8104 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec Oscilloscope ESD Gun 50 W Cable 50 W Figure 4. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8307/D − Characterization of ESD Clamping Performance. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger www.onsemi.com 3 ESD8104 20 −20 10 EQUIVALENT VIEC (kV) 8 −14 14 TLP CURRENT (A) −16 EQUIVALENT VIEC (kV) TLP CURRENT (A) 8 16 6 12 −12 6 −10 10 4 8 6 2 4 −8 4 −6 −4 2 −2 2 0 0 10 −18 18 2 4 6 8 10 12 14 VC, VOLTAGE (V) 16 18 0 0 20 0 2 Figure 5. Positive TLP I−V Curve NOTE: 4 6 8 10 12 14 VC, VOLTAGE (V) 16 0 20 18 Figure 6. Negative TLP I−V Curve TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description below for more information. Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 7. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 8 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. For more information on TLP measurements and how to interpret them please refer to AND9007/D. S Attenuator ÷ 50 W Coax Cable 10 MW IM 50 W Coax Cable VM DUT VC Oscilloscope Figure 7. Simplified Schematic of a Typical TLP System Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 4 ESD8104 Without ESD8104 With ESD8104 Figure 9. USB 3.0 Eye Diagram with and without ESD8104. 5 Gb/s Without ESD8104 With ESD8104 Figure 10. HDMI 2.0 Eye Diagram with and without ESD8104. 6 Gb/s Without ESD8104 With ESD8104 Figure 11. USB 3.1 Eye Diagram with and without ESD8104. 10 Gb/s See application note AND9075/D for further description of eye diagram testing methodology. www.onsemi.com 5 ESD8104 Figure 12. RF Insertion Loss TABLE 1. RF Insertion Loss: Application Description Interface Data Rate (Gb/s) Fundamental Frequency (GHz) 3rd Harmonic Frequency (GHz) ESD8104 Insertion Loss (dB) USB 3.0 5.0 2.5 (m1) 7.5 (m4) HDMI 2.0 6.0 3.0 (m2) 9.0 (m5) USB 3.1 10 5.0 (m3) 15 (m6) m1 = 0.128 m2 = 0.155 m3 = 0.352 m4 = 0.659 m5 = 0.958 m6 = 4.194 www.onsemi.com 6 ESD8104 USB 3.0/3.1 Type A Connector StdA_SSTX+ Vbus StdA_SSTX− ESD8104 D− ESD7L5.0 GND_DRAIN D+ StdA_SSRX+ GND StdA_SSRX− Figure 13. USB 3.0/3.1 Type−A Layout Diagram www.onsemi.com 7 Black = Top layer Red = Other layer ESD8104 Type−C Hybrid Top Mount Connector Top Layer GND TX1+ TX1− Vbus CC1 (Config. detect: Vconn or PD comm.) D+ D− SBU1 Sideband use: AUX signal Vbus RX2− RX2+ GND Type−C Hybrid Top Mount Connector Bottom Layer ESD9X GND RX1+ RX2+ SBU2 Vbus D− D+ Vbus CC2 TX2− TX2+ GND Black = Top layer Red = Bottom layer ESD9X Figure 14. USB 3.1 Type−C Layout Diagram www.onsemi.com 8 ESD8104 HDMI Type A Connector ESD8104 D2+ GND D2− D1+ GND D1− ESD8104 D0+ GND D0− CLK+ GND CLK− CEC N/C (or HEC_DAT) SCL SDA GND 5V HPD (and HEC_DAT) NUP4114 Figure 15. HDMI Layout Diagram www.onsemi.com 9 ESD8104 • Make sure to use differential design methodology and PCB Layout Guidelines Steps must be taken for proper placement and signal trace routing of the ESD protection device in order to ensure the maximum ESD survivability and signal integrity for the application. Such steps are listed below. • Place the ESD protection device as close as possible to the I/O connector to reduce the ESD path to ground and improve the protection performance. ♦ In USB 3.0/3.1 applications, the ESD protection device should be placed between the AC coupling capacitors and the I/O connector on the TX differential lanes as shown in Figure 16. impedance matching of all high speed signal traces. ♦ Use curved traces when possible to avoid unwanted reflections. ♦ Keep the trace lengths equal between the positive and negative lines of the differential data lanes to avoid common mode noise generation and impedance mismatch. ♦ Place grounds between high speed pairs and keep as much distance between pairs as possible to reduce crosstalk. Figure 16. USB 3.0/3.1 Connection Diagram www.onsemi.com 10 ESD8104 ESD Protection Device Technology ON Semiconductor’s portfolio contains three main technologies for low capacitance ESD protection device which are highlighted below and in Figure 17. • ESD7000 series: Zener diode based technology. This technology has a higher breakdown voltage (VBR) limiting it to protecting chipsets with larger geometries. • ESD8000 series: Silicon controlled rectifier (SCR) type technology. The key advatange for this technology is a low holding voltage (VH) which produces a deeper snapback that results in lower voltage over high • currents as shown in the TLP results in Figure 18. This technology provides optimized protection for chipsets with small geometries against thermal failures resulting in chipset damage (also known as “hard failures”). ESD8100 series: Low voltage punch through (LVPT) type technology. The key advatange for this technology is a very low turn-on voltage as shown in Figure 19. This technology provides optimized protection for chipsets with small geometries against recoverable failures due to voltage peaks (also known as “soft failures”). Figure 17. ON Semiconductor’s Low-cap ESD Technology Portfolio 10 20 18 TLP Current (A) 14 6 12 10 4 8 ESD8004 6 ESD8104 4 2 ESD7004 2 0 0 2 4 6 8 10 12 14 16 18 20 VC (V) Figure 18. High Current, TLP, IV Characteristic of Each Technology www.onsemi.com 11 0 Equivalent VIEC (kV) 8 16 ESD8104 1.00E−01 1.00E−02 ESD8004 1.00E−03 ESD8104 1.00E−04 ESD7004 I (A) 1.00E−05 1.00E−06 1.00E−07 1.00E−08 1.00E−09 1.00E−10 1.00E−11 0 1 2 3 4 5 6 7 V (V) Figure 19. Low Current, DC, IV Characteristic of Each Technology www.onsemi.com 12 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN10 2.5x1, 0.5P CASE 517BB−01 ISSUE O DATE 17 NOV 2009 SCALE 4:1 L L D PIN ONE REFERENCE 0.10 C 2X 2X A B L1 ÍÍÍ ÍÍÍ 0.10 C DETAIL A TOP VIEW EXPOSED Cu DETAIL B A3 0.10 C 10X OPTIONAL CONSTRUCTIONS E A A1 0.08 C A1 C SIDE VIEW 2X DETAIL A b2 1 10 10X MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 0.35 0.45 2.50 BSC 1.00 BSC 0.50 BSC 0.30 0.40 --0.05 GENERIC MARKING DIAGRAM* XXX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) b 0.10 C A 0.05 C BOTTOM VIEW A3 DIM A A1 A3 b b2 D E e L L1 XX MG G L 6 8X DETAIL B OPTIONAL CONSTRUCTION SEATING PLANE 5 e ÇÇ ÇÇ ÉÉ MOLD CMPD NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. B *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 10X 2X 0.50 0.45 1.30 PACKAGE OUTLINE 8X 0.50 PITCH 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON47059E UDFN10 2.5X1, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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