ESD8708MUTAG

ESD8708 ESD Protection Diode Low Capacitance Array for High Speed Data Lines The ESD8708 is designed specifically to protect four high speed differential pairs. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance for the high speed lines. Features • • • • • Integrated 4 Pairs (8 Lines) High Speed Data Single Connect, Flow through Routing Low Capacitance (0.5 pF Max, I/O to GND) Protection for the Following IEC Standards: IEC 61000−4−2 Level 4 (ESD) ±30 kV (Contact) IEC 61000−4−5 (Lightning) 6.5 A (8/20 ms) These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • • • • www.onsemi.com 1 8708M G UDFN14 CASE 517CN 8708 M G = Specific Device Code = Date Code = Pb−Free Package ORDERING INFORMATION Device ESD8708MUTAG Gigabit Ethernet V−by−One HS LVDS Display Port MARKING DIAGRAM 14 Package Shipping UDFN14 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range TJ −55 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C ESD ESD ±30 ±30 kV kV IPP 6.5 A IEC 61000−4−2 Contact (ESD) IEC 61000−4−2 Air (ESD) Maximum Peak Pulse Current 8/20 ms @ TA = 25°C (I/O−GND) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2016 June, 2019 − Rev. 0 1 Publication Order Number: ESD8708/D ESD8708 I/O Pin 1 I/O Pin 2 I/O Pin 4 I/O Pin 5 I/O Pin 7 I/O Pin 8 I/O Pin 10 I/O Pin 11 Center Pins, Pin 3, 6, 9, 12, 13, 14 Note: Common GND − Only Minimum of 1 GND connection required = Figure 1. Pin Schematic I/O 1 I/O 2 14 GND GND 3 I/O 4 I/O 5 13 GND GND 6 I/O 7 I/O 8 GND 9 12 GND I/O 10 I/O 11 Figure 2. Pin Configuration Note: Only minimum of one pin needs to be connected to ground for functionality of all pins. www.onsemi.com 2 ESD8708 I ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol VRWM IR VBR IT IPP Parameter RDYN Working Peak Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT VBR VHOLD Holding Reverse Voltage IHOLD Holding Reverse Current RDYN Dynamic Resistance V VC VRWMVHOLD Test Current IR IT VC IHOLD IPP Maximum Peak Pulse Current VC Clamping Voltage @ IPP VC = VHOLD + (IPP * RDYN) RDYN −IPP VC = VHOLD + (IPP * RDYN) ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage VRWM Breakdown Voltage VBR Conditions Min Typ 4.0 5.0 Max Unit 3.3 V 6.0 V I/O Pin to GND IT = 1 mA, I/O Pin to GND Holding Reverse Voltage VHOLD I/O Pin to GND 1.19 V Holding Reverse Current IHOLD I/O Pin to GND 20 mA 7.5 A Reverse Peak Current IPP IEC61000−4−5 (8/20 ms) Clamping Voltage (Note 1) VC IEC61000−4−2, ±8 KV Contact Clamping Voltage VC IPP = 1.5 A, Any I/O to GND (8/20 ms pulse) 2.6 3.2 V Clamping Voltage VC IPP = 5 A, Any I/O to GND (8/20 ms pulse) 3.9 5.2 V Clamping Voltage VC IPP = 6.5 A, Any I/O to GND (8/20 ms pulse) 4.9 6.8 V Clamping Voltage TLP (Note 2) See Figures 7 through 10 VC IPP = 8 A IPP = −8 A IEC 61000−4−2 Level 2 equivalent (±4 kV Contact, ±4 kV Air) 4.5 −3.8 IPP = 16 A IPP = −16 A IEC 61000−4−2 Level 4 equivalent (±8 kV Contact, ±15 kV Air) 6.5 −6.3 Dynamic Resistance RDYN Junction Capacitance CJ 6.5 See Figures 3 and 4 I/O Pin to GND GND to I/O Pin 0.25 0.31 VR = 0 V, f = 1 MHz between I/O Pins and GND VR = 0 V, f = 2.5 GHz between I/O Pins and GND VR = 0 V, f = 5.0 GHz between I/O Pins and GND VR = 0 V, f = 1 MHz, between I/O Pins 0.34 0.30 0.31 0.18 V V W 0.5 pF 0.25 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. For test procedure see Figures 5 and 6 and application note AND8307/D. 2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 1 ns, averaging window; t1 = 70 ns to t2 = 90 ns. 10 80 0 70 −10 60 −20 VOLTAGE (V) VOLTAGE (V) 90 50 40 30 20 −40 −50 −60 −70 10 −80 0 −10 −20 −30 −90 0 20 40 60 80 100 120 −100 −20 140 TIME (ns) 0 20 40 60 80 100 120 TIME (ns) Figure 3. IEC61000−4−2 +8 kV Contact ESD Clamping Voltage Figure 4. IEC61000−4−2 −8 kV Contact Clamping Voltage www.onsemi.com 3 140 ESD8708 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 5. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 6. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8307/D − Characterization of ESD Clamping Performance. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger www.onsemi.com 4 20 −20 18 −18 16 −16 TLP CURRENT (A) TLP CURRENT (A) ESD8708 14 12 10 8 6 −14 −12 −10 −8 −6 4 −4 2 −2 0 0 1 2 3 4 5 6 7 8 0 9 10 11 12 13 14 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 VC, VOLTAGE (V) VC, VOLTAGE (V) Figure 7. Positive TLP I−V Curve Figure 8. Negative TLP I−V Curve Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 9. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 10 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. For more information on TLP measurements and how to interpret them please refer to AND9007/D. 50 W Coax Cable S Attenuator ÷ 50 W Coax Cable 10 MW IM VM DUT VC Oscilloscope Figure 9. Simplified Schematic of a Typical TLP System Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 5 ESD8708 Peak Value 100 6 5 Vpk (V) Ipp - PEAK PULSE CURRENT - %Ipp 7 tr = rise time to peak value [8 ms] tf = decay time to half value [20 ms] Half Value 50 4 3 2 1 0 0 tr 0 tf 0 1 2 3 TIME (ms) 4 6 5 IPP (A) 7 8 9 10 Figure 12. Clamping Voltage vs. Peak Pulse Current (tp = 8/20 ms per Figure 11) Figure 11. IEC61000−4−5 8/20 ms Pulse Waveform 1.0 0.0 0.9 −0.5 S(2,1) Magnitude (dB) 0.8 C (pF) 0.7 0.6 0.5 0.4 0.3 0.2 −1.5 −2.0 −2.5 0.1 0 1.E+07 −1.0 1.E+10 1.E+08 1.E+09 Frequency (Hz) −3.0 1.E+07 1.E+08 1.E+09 Frequency (Hz) Figure 14. Insertion Loss Figure 13. Capacitance over Frequency 1 ESD8708 2 3 5 6 7 8 Figure 15. Gigabit Ethernet www.onsemi.com 6 RJ−45 Connector 4 1.E+10 ESD8708 ESD8708 Rx0p Rx0n Rx1p Rx1n Rx2p Rx2n Rx3p ESD8708 Rx4p TCON Board Connector Timing Controller Rx3n Rx4n Rx5p Rx5n Rx6p Rx6n Rx7p Rx7n Figure 16. V−by−One HS Layout Diagram (for LCD Panel) PCB Layout Guidelines ♦ Steps must be taken for proper placement and signal trace routing of the ESD protection device in order to ensure the maximum ESD survivability and signal integrity for the application. Such steps are listed below. • Place the ESD protection device as close as possible to the I/O connector to reduce the ESD path to ground and improve the protection performance. • Make sure to use differential design methodology and impedance matching of all high speed signal traces. ♦ ♦ Use curved traces when possible to avoid unwanted reflections. Keep the trace lengths equal between the positive and negative lines of the differential data lanes to avoid common mode noise generation and impedance mismatch. Place grounds between high speed pairs and keep as much distance between pairs as possible to reduce crosstalk. www.onsemi.com 7 ESD8708 Latch-Up Considerations stable operating point of the circuit and the system is therefore latch-up free. In the non-latch up free load line case, the IV characteristic of the snapback protection device intersects the load-line in two points (VOPA, IOPA) and (VOPB, IOPB). Therefore in this case, the potential for latch-up exists if the system settles at (VOPB, IOPB) after a transient. Because of this, ESD8708 should not be used for HDMI applications – ESD8104 or ESD8040 have been designed to be acceptable for HDMI applications without latch-up. Please refer to Application Note AND9116/D for a more in-depth explanation of latch-up considerations using ESD8000 series devices. ON Semiconductor’s 8000 series of ESD protection devices utilize a snap-back, SCR type structure. By using this technology, the potential for a latch-up condition was taken into account by performing load line analyses of common high speed serial interfaces. Example load lines for latch-up free applications and applications with the potential for latch-up are shown below with a generic IV characteristic of a snapback, SCR type structured device overlaid on each. In the latch-up free load line case, the IV characteristic of the snapback protection device intersects the load-line in one unique point (VOP, IOP). This is the only I I ISSMAX IOPB ISSMAX IOP VOP IOPA V VDD VOPB ESD8708 Latch−up free: V−by−One HS, DisplayPort, LVDS VOPA VDD V ESD8708 Potential Latch−up: HDMI 1.4/1.3a TMDS Figure 17. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS Application VBR (min) (V) IH (min) (mA) VH (min) (V) ON Semiconductor ESD8000 Series Recommended PN HDMI TMDS 3.465 54.78 1.0 ESD8104, ESD8040 DisplayPort 3.600 25.00 1.0 ESD8004, ESD8006, ESD8708 V−by−One HS 1.980 21.70 1.0 ESD8708 LVDS 1.829 9.20 1.0 ESD8708 www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN14, 5.5x1.5, 0.5P CASE 517CN ISSUE O 14 1 SCALE 2:1 DATE 30 OCT 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.10 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L PIN ONE REFERENCE 2X 0.10 C 2X A B D ÉÉ 0.10 C L1 DETAIL A OPTIONAL CONSTRUCTION E TOP VIEW (A3) DETAIL B 0.05 C EXPOSED Cu A 0.10 C ÉÉ ÇÇ MOLD CMPD DETAIL B NOTE 4 A1 SIDE VIEW e DETAIL C 12 D2 C 0.10 REF 14 BOTTOM VIEW M C A B 0.05 M C NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 6X 3X XXXXM G DETAIL C b 0.10 0.43 0.56 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 5.50 BSC 0.45 0.55 1.50 BSC 0.50 0.70 0.50 BSC 0.20 0.40 0.00 0.05 GENERIC MARKING DIAGRAM* L 11 14X PACKAGE OUTLINE OPTIONAL CONSTRUCTION SEATING PLANE DETAIL A 1 E2 DIM A A1 A3 b D D2 E E2 e L L1 XXXX M G = Specific Device Code = Date Code = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. 1.80 3X 0.62 14X 0.50 PITCH 0.26 14X 0.50 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON84523E UDFN14, 5.5X1.5, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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