ESD9B3.3ST5G

ESD9B3.3ST5G Transient Voltage Suppressors Micro−Packaged Diodes for ESD Protection The ESD9B Series is designed to protect voltage sensitive components from ESD. Excellent clamping capability, low leakage, and fast response time provide best in class protection on designs that are exposed to ESD. Because of its small size, it is suited for use in cellular phones, MP3 players, digital cameras and many other portable applications where board space comes at a premium. Specification Features http://onsemi.com • • • • • • • • • Low Capacitance 15 pF Low Clamping Voltage Small Body Outline Dimensions: 0.039″ x 0.024″ (1.0mm x 0.60mm) Low Body Height: 0.016″ (0.4 mm) Stand−off Voltage: 3.3 V Low Leakage Response Time is < 1 ns IEC61000−4−2 Level 4 ESD Protection This is a Pb−Free Device SOD−923 CASE 514AB MARKING DIAGRAM XM Mechanical Characteristics CASE: Void-free, transfer-molded, thermosetting plastic Epoxy Meets UL 94 V−0 LEAD FINISH: 100% Matte Sn (Tin) MOUNTING POSITION: Any QUALIFIED MAX REFLOW TEMPERATURE: 260°C X M = Specific Device Code Date Code Device Meets MSL 1 Requirements MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) ORDERING INFORMATION Device Symbol Value ±8.0 ±15 °PD° RqJA TJ, Tstg TL 300 400 −55 to +150 260 Unit kV mW °C/W °C °C ESD9B3.3ST5G Package SOD−923 (Pb−Free) Shipping† 8000/Tape & Reel Contact Air Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Thermal Resistance, Junction−to−Ambient Junction and Storage Temperature Range Lead Solder Temperature − Maximum (10 Second Duration) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. FR−5 = 1.0 x 0.75 x 0.62 in. © Semiconductor Components Industries, LLC, 2008 September, 2008 − Rev. 0 1 Publication Order Number: ESD9B3.3S/D ESD9B3.3ST5G ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol IPP VC VRWM IR VBR IT C Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current Capacitance @ VR = 0 V and f = 1.0 MHz IPP IT VC VBR VRWM IR IR VRWM VBR VC IT IPP I V Bi−Directional TVS ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) VRWM (V) Device ESD9B3.3ST5G Device Marking 2* Max 3.3 IR (mA) @ VRWM Max 1.0 VBR (V) @ IT (Note 2) Min 5.0 Max 7.0 IT mA 1.0 C (pF) Typ 15 VC Per IEC61000−4−2 (Note 3) Figures 1 and 2 See Below VC (V) @ IPP = 1 A Max Per 8 x 20 ms (Note 4) 10.5 * Rotated 270°. 2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C. 3. For test procedure see Figures 3 and 4 and Application Note AND8307/D. 4. Surge current waveforms per Figure 5. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 http://onsemi.com 2 ESD9B3.3ST5G IEC 61000−4−2 Spec. Test Voltage (kV) 2 4 6 8 First Peak Current (A) 7.5 15 22.5 30 Current at 30 ns (A) 4 8 12 16 Current at 60 ns (A) 2 4 6 8 I @ 60 ns 10% tP = 0.7 ns to 1 ns I @ 30 ns IEC61000−4−2 Waveform Ipeak 100% 90% Level 1 2 3 4 Figure 3. IEC61000−4−2 Spec ESD Gun TVS Oscilloscope 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger 100 % OF PEAK PULSE CURRENT 90 80 70 60 50 40 30 20 10 0 0 20 tP tr systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. PEAK VALUE IRSM @ 8 ms PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms HALF VALUE IRSM/2 @ 20 ms Figure 5. 8 X 20 ms Pulse Waveform 40 t, TIME (ms) 60 80 http://onsemi.com 3 ESD9B3.3ST5G PACKAGE DIMENSIONS SOD−923 CASE 514AB−01 ISSUE B D −X− −Y− E 1 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A b c D E HE L MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 0.15 0.20 0.25 0.07 0.12 0.17 0.75 0.80 0.85 0.55 0.60 0.65 0.95 1.00 1.05 0.05 0.10 0.15 MIN 0.013 0.006 0.003 0.030 0.022 0.037 0.002 INCHES NOM 0.015 0.008 0.005 0.031 0.024 0.039 0.004 MAX 0.016 0.010 0.007 0.033 0.026 0.041 0.006 b 2X 0.08 (0.0032) X Y A c L HE SOLDERING FOOTPRINT* 0.90 0.40 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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