ESDL2011
ESD Protection Diode
Micro−Packaged Diodes for ESD Protection
The ESDL2011 is designed to protect voltage sensitive components
that require low capacitance from ESD and transient voltage events.
Excellent clamping capability, low capacitance, low leakage, and fast
response time, make these parts ideal for ESD protection on designs
where board space is at a premium. Because of its low capacitance, the
part is well suited for use in high speed data line applications.
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1
Features
•
•
•
•
•
•
•
Low Capacitance 0.17 pF (Typ)
Low Clamping Voltage
Small Body Outline Dimensions: 0.60 mm x 0.30 mm
Low Body Height: 0.2 mm
Stand−off Voltage: 1.0 V
IEC61000−4−2 Level 4 ESD Protection
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
2
MARKING
DIAGRAM
DSN2
(Side wall isolated)
CASE 152AX
A
A
= Specific Device Code
Typical Applications
• USB 3.x
• Thunderbolt 3.0
ORDERING INFORMATION
MAXIMUM RATINGS
Rating
IEC 61000−4−2 (ESD)
Symbol
Contact
Air
Value
Unit
±15
±15
kV
Total Power Dissipation on FR−4 Board
(Note 1) @ TA = 25°C
Thermal Resistance, Junction−to−Ambient
°PD°
313
mW
RqJA
400
°C/W
Junction and Storage Temperature Range
TJ, Tstg
−55 to +150
°C
TL
260
°C
Lead Solder Temperature − Maximum
(10 Second Duration)
Device
Package
Shipping†
ESDL2011PFCT5G
DSN2
(Pb−Free)
10000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−4 = 28 mm2 1 oz. Cu JEDEC JESD51−3 two layer PCB.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2017
May, 2019 − Rev. 2
1
Publication Order Number:
ESDL2011/D
ESDL2011
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
IPP
I
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IT
VC VBR VRWM IR
IR VRWM VBR VC
IT
Working Peak Reverse Voltage
IR
V
Maximum Reverse Leakage Current @ VRWM
VBR
Breakdown Voltage @ IT
IT
IPP
Test Current
Bi−Directional Surge Protector
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Reverse Working Voltage
Breakdown Voltage
VRWM
VBR
Conditions
Min
Typ
1.4
1.65
30
I/O Pin to GND
IT = 1 mA, I/O Pin to GND
Max
Unit
1.0
V
2.3
V
500
nA
Reverse Leakage Current
IR
VRWM = 1.0 V
Clamping Voltage (Note 2)
VC
IEC61000−4−2, ±8 kV Contact
Clamping Voltage
200 ns TLP
VC
IPP = 4 A
IEC61000−4−2 Level 1 Equivalent
(±2 kV Contact, ±4 kV Air)
3.5
4.0
IPP = 8 A
IEC61000−4−2 Level 2 Equivalent
(±4 kV Contact, ±8 kV Air)
4.8
6.0
Figures 1 and 2
3.5
V
V
Reverse Peak Pulse Current
per Figure 12
IPP
per IEC61000−4−5 (1.2/50 ms), Req = 12 W
4.5
A
Clamping Voltage 1.2/50 ms
Waveform per Figure 12
VC
IPP = 2.1 A, IEC61000−4−5 (1.2/50 ms),
Req = 12 W
2.9
3.5
V
Clamping Voltage 1.2/50 ms
Waveform per Figure 12
VC
IPP = 3.5 A, IEC61000−4−5 (1.2/50 ms),
Req = 12 W
3.6
4.0
V
Dynamic Resistance (TLP)
RDYN
I/O Pin to GND (4 A to 8 A, 200 ns TLP)
0.34
0.5
W
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz
0.17
0.20
pF
Insertion Loss
IL
f = 5 GHz
f = 10 GHz
0.165
0.34
0.20
0.40
dB
100
10
90
0
80
−10
70
−20
60
−30
VOLTAGE (V)
VOLTAGE (V)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. For test procedure see application note AND8307/D.
3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 200 ns, tr = 4 ns, averaging window; t1 = 170 ns to t2 = 190 ns.
50
40
30
−40
−50
−60
20
−70
10
−80
−90
0
−10
−25
0
25
50
75
TIME (ns)
100
125
−100
−25
150
Figure 1. IEC61000−4−2 + 8 kV Contact ESD
Clamping Voltage
0
25
50
75
TIME (ns)
100
125
Figure 2. IEC61000−4−2 − 8 kV Contact ESD
Clamping Voltage
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2
150
ESDL2011
TYPICAL CHARACTERISTICS
1.E−02
1.E−03
1.E−04
IR (A)
1.E−05
1.E−06
1.E−07
1.E−08
1.E−09
1.E−10
1.E−11
1.E−12
1.E−13
1.E−14
−1.5
−1
−0.5
0
0.5
1
1.5
VR (V)
Figure 3. IV Characteristics
1.0
−0.1
0.9
−0.2
0.8
CAPACITANCE (pF)
0
S21 (dB)
−0.3
−0.4
−0.5
−0.6
−0.7
0.7
0.6
0.5
0.4
0.3
−0.8
0.2
−0.9
0.1
−1.0
1.E+07
1.E+08
1.E+09
0
0.E+00
1.E+10
0 1
2
3
4
5
6
7
8
1.E+10
2.E+10
3.E+10
Figure 5. Typical Capacitance over Frequency
ITLP (A)
ITLP (A)
Figure 4. Insertion Loss
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
5.E+09
FREQUENCY (Hz)
FREQUENCY (Hz)
9 10 11 12 13 14 15 16
−16
−15
−14
−13
−12
−11
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10−11−12−13−14−15−16
VOLTAGE (V)
VOLTAGE (V)
Figure 6. Positive 200 ns TLP IV Curve
Figure 7. Negative 200 ns TLP IV Curve
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3
ESDL2011
5.0
5.0
4.5
4.5
4.0
4.0
3.5
3.5
VC @ IPK (V)
VC @ IPK (V)
TYPICAL CHARACTERISTICS
3.0
2.5
2.0
1.5
3.0
2.5
2.0
1.5
1.0
1.0
0.5
0.5
0.0
0.0
0.5
1.0
1.5
2.0
2.5 3.0
IPK (A)
3.5
4.0
4.5
0.0
0.0
5.0
Figure 8. Positive Clamping Voltage vs. Peak Pulse
Current (per IEC61000−4−5 (tp = 1.2/50 ms, Req = 12 W))
0.5
1.0
1.5
2.0
2.5 3.0
IPK (A)
3.5
4.0
4.5
5.0
Figure 9. Negative Clamping Voltage vs. Peak Pulse
Current (per IEC61000−4−5 (tp = 1.2/50 ms, Req = 12 W))
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ESDL2011
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 10. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 11. Diagram of ESD Test Setup
ESD Voltage Clamping
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Vp, PEAK VOLTAGE (%Vp)
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
tr = rise time to peak value [1.2 ms]
tf = decay time to half value [50 ms]
Peak
Value
100
Half Value
50
0
0 tr
tf
t, TIME (ms)
Figure 12. IEC61000−4−5 1.2/50 ms Pulse
Waveform
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
X4DFN2, 0.60x0.30, 0.36P
CASE 152AX
ISSUE G
SCALE 8:1
D
PIN 1
INDICATOR
ÈÈ
DATE 12 APR 2019
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
E
DIM
A
A1
b
D
E
e
L
TOP VIEW
A
0.02 C
A1
GENERIC
MARKING DIAGRAM*
0.01 C
C
SIDE VIEW
MILLIMETERS
MIN
NOM MAX
0.175 0.200 0.225
0.018 REF
0.205 0.215 0.225
0.575 0.600 0.625
0.275 0.300 0.325
0.36 BSC
0.145 0.155 0.165
SEATING
PLANE
X
e
X
b
X = Specific Device Code
1
0.05
M
2X L
C A B
0.05
M
C A B
BOTTOM VIEW
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present. Some products may
not follow the Generic Marking.
RECOMMENDED
SOLDER FOOTPRINT*
0.65
2X
1
2X
0.27
0.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON06808G
X4DFN2, 0.60x0.30, 0.36P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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