ESDM3551N2T5G

DATA SHEET www.onsemi.com 5.5 V ESD Protection Diode Micro−Packaged Diodes for ESD Protection X3DFN2 (0201) CASE 152AF ESDM3551 The ESDM3551 is designed to protect voltage sensitive components that require low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. X2DFN2 (0402) CASE 714AB MARKING DIAGRAMS Features • Low Clamping Voltage • Small Body Outline Dimensions: • • • • • 5 PIN 1 − 0201: 0.62 mm x 0.32 mm − 0402: 1.00 mm x 0.60 mm Low Body Height: 0.3 mm Stand−off Voltage: 5.5 V IEC61000−4−2 Level 4 ESD Protection SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 5 M M = Specific Device Code = Date Code JJ M JJ = Specific Device Code M = Date Code Typical Applications • • • • USB ID Line Protection mSD Card Protection Audio Line Protection GPIO ORDERING INFORMATION MAXIMUM RATINGS Rating Symbol Value Unit IEC 61000−4−2 Contact IEC 61000−4−2 Air ISO 10605 150 pF/2 kW ISO 10605 330 pF/2 kW ISO 10605 330 pF/330 W ESD ±30 ±30 ±30 ±30 ±30 kV Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Thermal Resistance, Junction−to−Ambient °PD° 250 mW RqJA 400 °C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C TL 260 °C Lead Solder Temperature − Maximum (10 Second Duration) 2 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. FR−5 = 1.0 x 0.75 x 0.62 in. Device Package Shipping† ESDM3551MXT5G X3DFN2 (Pb−Free) 10000 / Tape & Reel ESDM3551N2T5G X2DFN2 (Pb−Free) 8000 / Tape & Reel SZESDM3551N2T5G X3DFN2 (Pb−Free) 8000 / Tape & Reel SZESDM3551MXT5G X3DFN2 (Pb−Free) 10000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2017 September, 2022 − Rev. 5 1 Publication Order Number: ESDM3551/D ESDM3551 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) IPP I Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IT VC VBR VRWM IR IR VRWM VBR VC IT Working Peak Reverse Voltage IR V Maximum Reverse Leakage Current @ VRWM VBR Breakdown Voltage @ IT IT IPP Test Current Bi−Directional TVS *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage Conditions Min Typ VRWM Breakdown Voltage (Note 2) VBR IT = 1 mA 5.6 Max Unit 5.5 V 7.0 V Reverse Leakage Current IR VRWM = 5.5 V 0.1 mA Clamping Voltage (Note 3) VC IPP = 1 A 6.0 V Clamping Voltage (Note 3) VC IPP = 8 A 8.2 V Peak Pulse Current (Note 3) IPP tP = 8/20 ms Clamping Voltage TLP (Note 4) VC IPP = 16 A Junction Capacitance CJ VR = 0 V, f = 1 MHz Dynamic Resistance RDYN Insertion Loss 9.9 A 7.5 IEC 61000−4−2 Level 4 equivalent (±8 kV Contact, ±15 kV Air) V 21 pF TLP Pulse 0.11 W f = 10 MHz 0.01 dB Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 3. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform. 4. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. 40 5 35 0 30 −5 25 −10 VOLTAGE (V) VOLTAGE (V) TYPICAL CHARACTERISTICS 20 15 10 −15 −20 −25 5 −30 0 −35 −5 −20 0 20 40 60 80 TIME (ns) 100 −40 −20 120 140 Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 0 20 40 60 80 TIME (ns) 100 120 140 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 www.onsemi.com 2 ESDM3551 TYPICAL CHARACTERISTICS (continued) 1.E−03 25 1.E−04 20 1.E−05 1.E−06 IR (A) C (pF) 15 1.E−07 10 1.E−08 1.E−09 5 1.E−10 1.E−11 −10 −8 −6 −4 −2 0 2 4 6 0 −5 10 8 −4 −3 −2 −1 VR (V) Figure 3. IV Characteristics 0 3 4 5 70.0 60.0 CAPACITANCE (pF) −2 −3 −4 −5 −6 −7 50.0 40.0 30.0 20.0 −8 10.0 −9 −10 1.0E+07 1.0E+08 0.0 0.0E+00 1.0E+09 5.0E+08 1.0E+09 1.5E+09 2.0E+09 FREQUENCY FREQUENCY (Hz) Figure 5. RF Insertion Loss Figure 6. Capacitance over Frequency 20 10 10 −20 18 8 14 12 6 10 8 4 6 4 2 EQUIVALENT VIEC (kV) TLP CURRENT (A) −18 16 2 8 −16 −14 −12 6 −10 −8 4 −6 −4 2 −2 1 2 3 4 5 6 7 8 9 0 0 10 0 1 2 3 4 5 6 7 8 VOLTAGE (V) VOLTAGE (V) Figure 7. Positive TLP I−V Curve Figure 8. Negative TLP I−V Curve www.onsemi.com 3 9 0 10 EQUIVALENT VIEC (kV) S21 (dB) 2 80.0 −1 TLP CURRENT (A) 1 Figure 4. CV Characteristics 1 0 0 0 VBIAS (V) ESDM3551 TYPICAL CHARACTERISTICS (continued) 10 9 9 8 8 7 VC @ IPK (V) VC @ IPK (V) 7 6 5 4 3 6 5 4 3 2 2 1 1 0 0 2 4 6 8 10 0 0 12 2 4 6 8 10 12 IPK (A) IPK (A) Figure 9. Positive Clamping Voltage vs. Peak Pulse Current (tp = 8/20 ms) Figure 10. Negative Clamping Voltage vs. Peak Pulse Current (tp = 8/20 ms) www.onsemi.com 4 ESDM3551 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 11. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 12. Diagram of ESD Test Setup ESD Voltage Clamping clearly defined in the spec how to specify a clamping voltage at the device level. onsemi has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how onsemi creates these screenshots and how to interpret them please refer to AND8307/D. For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 13. 8 X 20 ms Pulse Waveform www.onsemi.com 5 80 ESDM3551 Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 14. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 15 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. 50 W Coax Cable S Attenuator ÷ 50 W Coax Cable 10 MW IM VM DUT VC Oscilloscope Figure 14. Simplified Schematic of a Typical TLP System Figure 15. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS X3DFN2, 0.62x0.32, 0.355P, (0201) CASE 152AF ISSUE A DATE 17 FEB 2015 SCALE 8:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. A B D PIN 1 INDICATOR (OPTIONAL) DIM A A1 b D E e L2 E TOP VIEW 0.05 C A 2X 0.05 C A1 SIDE VIEW C MILLIMETERS MIN MAX 0.25 0.33 −−− 0.05 0.22 0.28 0.58 0.66 0.28 0.36 0.355 BSC 0.17 0.23 GENERIC MARKING DIAGRAM* SEATING PLANE PIN 1 XM e 1 2X 0.05 M 2 2X b X = Specific Device Code M = Date Code 0.05 L2 M C A B RECOMMENDED MOUNTING FOOTPRINT* C A B BOTTOM VIEW 0.74 2X 0.30 1 2X 0.31 DIMENSIONS: MILLIMETERS See Application Note AND8398/D for more mounting details *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON56472E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. X3DFN2, 0.62X0.32, 0.355P, (0201) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS X2DFN2 1.0x0.6, 0.65P CASE 714AB ISSUE B DATE 21 NOV 2017 SCALE 8:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. EXPOSED COPPER ALLOWED AS SHOWN. 0.10 C A B D É PIN 1 INDICATOR E DIM A A1 b D E e L 0.05 C TOP VIEW A NOTE 3 0.10 C 0.10 C A1 C SIDE VIEW GENERIC MARKING DIAGRAM* SEATING PLANE XX M e b e/2 MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 −−− 0.03 0.05 0.45 0.50 0.55 0.95 1.00 1.05 0.55 0.60 0.65 0.65 BSC 0.20 0.25 0.30 0.05 M XX = Specific Device Code M = Date Code C A B RECOMMENDED SOLDER FOOTPRINT* 1 2X L 0.05 M C A B BOTTOM VIEW 1.20 2X 0.47 2X 0.60 PIN 1 DIMENSIONS: MILLIMETERS *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON98172F X2DFN2 1.0X0.6, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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