FAM65CR51DZ2

Boost Converter Stage in APM16 Series for Multiphase and Semi-Bridgeless PFC FAM65CR51DZ1, FAM65CR51DZ2 www.onsemi.com Features • Integrated SIP or DIP Boost Converter Stage Power Module for • • • • • • On−board Charger (OBC) in EV or PHEV 5 kV/1 sec Electrically Isolated Substrate for Easy Assembly Creepage and Clearance per IEC60664−1, IEC 60950−1 Compact Design for Low Total Module Resistance Module Serialization for Full Traceability Lead Free, RoHS and UL94V−0 Compliant Automotive Qualified per AEC Q101 and AQG324 Guidelines APMCD−A16 12 LEAD CASE MODGG Applications • PFC Stage of an On−board Charger in PHEV or EV Benefits • Enable Design of Small, Efficient and Reliable System for Reduced Vehicle Fuel Consumption and CO2 Emission • Simplified Assembly, Optimized Layout, High Level of Integration, and Improved Thermal Performance APMCD−B16 12 LEAD CASE MODGK MARKING DIAGRAM XXXXXXXXXXX ZZZ ATYWW NNNNNNN XXXX ZZZ AT Y W NNN = Specific Device Code = Lot ID = Assembly & Test Location = Year = Work Week = Serial Number ORDERING INFORMATION See detailed ordering, marking and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2018 June, 2021 − Rev. 3 1 Publication Order Number: FAM65CR51DZ1/D FAM65CR51DZ1, FAM65CR51DZ2 ORDERING INFORMATION Pb−Free and Operating RoHS Compliant Temperature (TA) Packing Method Part Number Package Lead Forming DBC Material FAM65CR51DZ1 APM16−CDA Y−Shape Al2O3 Yes −40°C ~ 125°C Tube FAM65CR51DZ2 APM16−CDB L−Shape Al2O3 Yes −40°C ~ 125°C Tube Pin Configuration and Description Figure 1. Pin Configuration Table 1. PIN DESCRIPTION Pin Number Pin Name Pin Description 1, 2 AC1 Phase 1 Leg of the PFC Bridge 3 NC Not Connected 4 NC Not Connected 5, 6 B+ Positive Battery Terminal 7, 8 Q1 Source Source Terminal of Q1 9 Q1 Gate Gate Terminal of Q1 10 Q2 Gate Gate Terminal of Q2 11, 12 Q2 Source Source Terminal of Q2 13 NC Not Connected 14 NC Not Connected 15, 16 AC2 Phase 2 Leg of the PFC Bridge www.onsemi.com 2 FAM65CR51DZ1, FAM65CR51DZ2 INTERNAL EQUIVALENT CIRCUIT Figure 2. Internal Block Diagram Table 2. ABSOLUTE MAXIMUM RATINGS OF MOSFET (TJ = 25°C, Unless Otherwise Specified) Max Unit VDS (Q1~Q2) Drain−to−Source Voltage Parameter 650 V VGS (Q1~Q2) Gate−to−Source Voltage ±20 V Drain Current Continuous (TC = 25°C, VGS = 10 V) (Note 1) 33 A Drain Current Continuous (TC = 100°C, VGS = 10 V) (Note 1) 23 A Single Pulse Avalanche Energy (Note 2) 623 mJ Symbol ID (Q1~Q2) EAS (Q1~Q2) PD Power Dissipation (Note 1) 160 W TJ Maximum Junction Temperature −55 to +150 °C TC Maximum Case Temperature −40 to +125 °C Storage Temperature −40 to +125 °C TSTG Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Maximum continuous current and power, without switching losses, to reach TJ = 150°C respectively at TC = 25°C and TC = 100°C; defined by design based on MOSFET RDS(ON) and RqJC and not subject to production test 2. Starting TJ = 25°C, IAS = 6.5 A, RG = 25 W DBC Substrate Compliance to RoHS Directives 0.63 mm Al2O3 alumina with 0.3 mm copper on both sides. DBC substrate is NOT nickel plated. The power module is 100% lead free and RoHS compliant 2000/53/C directive. Lead Frame Solder OFC copper alloy, 0.50 mm thick. Plated with 8 um to 25.4 um thick Matte Tin Solder used is a lead free SnAgCu alloy. Solder presents high risk to melt at temperature beyond 210°C. Base of the leads, at the interface with the package body, should not be exposed to more than 200°C during mounting on the PCB or during welding to prevent the re−melting of the solder joints. Flammability Information All materials present in the power module meet UL flammability rating class 94V−0. www.onsemi.com 3 FAM65CR51DZ1, FAM65CR51DZ2 Table 3. ELECTRICAL SPECIFICATIONS OF MOSFET (TJ = 25°C, Unless Otherwise Specified) Symbol Parameter Conditions Min Typ Max Unit BVDSS Drain−to−Source Breakdown Voltage ID = 1 mA, VGS = 0 V 650 − − V VGS(th) Gate−to−Source Threshold Voltage VGS = VDS, ID = 3.3 mA 3.0 − 5.0 V VGS = 10 V, ID = 20 A − 44 51 mW − 44 51 mW − 79 − mW − 79 − mW VDS = 20 V, ID = 20 A (Note 3) − 30 − S RDS(ON) Q1 Q1 Low Side MOSFET RDS(ON) Q2 Q2 Low Side MOSFET RDS(ON) Q1 Q1 Low Side MOSFET RDS(ON) Q2 Q2 Low Side MOSFET VGS = 10 V, ID = 20 A, TJ = 125°C (Note 3) gFS Forward Transconductance IGSS Gate−to−Source Leakage Current VGS = ±20 V, VDS = 0 V −100 − +100 nA IDSS Drain−to−Source Leakage Current VDS = 650 V, VGS = 0 V − − 10 mA VDS = 400 V VGS = 0 V f = 1 MHz − 4864 − pF − 109 − pF − 16 − pF VDS = 0 to 520 V VGS = 0 V − 652 − pF DYNAMIC CHARACTERISTICS (Note 3) Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Coss(eff) Effective Output Capacitance Rg Qg(tot) Gate Resistance Total Gate Charge Qgs Gate−to−Source Gate Charge Qgd Gate−to−Drain “Miller” Charge f = 1 MHz − 2 − W VDS = 380 V ID = 20 A VGS = 0 to 10 V − 123 − nC − 37.5 − nC − 49 − nC VDS = 400 V ID = 20 A VGS = 10 V RG = 4.7 Ohm − 87 − ns − 47 − ns SWITCHING CHARACTERISTICS (Note 3) ton Turn−on Time td(on) Turn−on Delay Time tr Turn−on Rise Time toff td(off) tf − 43 − ns Turn−off Time − 148 − ns Turn−off Delay Time − 118 − ns Turn−off Fall Time − 29 − ns ISD = 20 A, VGS = 0 V − 0.95 − V VDS = 520 V, ID = 20 A, dI/dt = 100 A/ms (Note 3) − 133 − ns − 669 − nC BODY DIODE CHARACTERISTICS VSD Source−to−Drain Diode Voltage Trr Reverse Recovery Time Qrr Reverse Recovery Charge Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Defined by design, not subject to production test www.onsemi.com 4 FAM65CR51DZ1, FAM65CR51DZ2 Table 4. ABSOLUTE MAXIMUM RATINGS OF THE BOOST DIODE (TJ = 25°C, Unless Otherwise Specified) Parameter Symbol Rating Unit VRRM Peak Repetitive Reverse Voltage (Note 4) 600 V VRWM Working Peak Reverse Voltage (Note 4) 600 V DC Blocking Voltage 600 V IF(AV) Average Rectified Forward Current TC = 25°C 15 A IFSM Non−Repetitive Peak Surge Current (Half Wave 1 Phase 60 Hz) 45 A VR TJ Maximum Junction Temperature −55 to +175 °C TC Maximum Case Temperature −40 to +125 °C TSTG Storage Temperature −40 to +125 °C EAVL Avalanche Energy (2.85 A, 1 mH) 4 mJ 4. VRRM and IF(AV) value referenced to TO220−2L Auto Qualified Package Device ISL9R1560P_F085 Table 5. ELECTRICAL SPECIFICATIONS OF THE BOOST DIODE (TJ = 25°C, Unless Otherwise Specified) Parameter Symbol IR VFM Test Conditions Instantaneous Reverse Current VR = 600 V Instantaneous Forward Voltage (Note 5) IF=15 A trr Reverse Recovery Time ta Time to reach peak reverse current tb Time from peak IRRM to projected zero crossing of IRRM based on a straight line from peak IRRM through 25% of IRRM Qrr Reverse Recovered Charge IF = 15 A dIF/dt = 200 A/ms VR=390 V (Note 3) Min Typ Max Unit TC = 25°C − − 100 mA TC = 125°C − − 1 mA TC = 25°C − 1.65 2.2 V TC = 125°C − 1.24 1.7 V TC = 25°C − 29 − ns TC = 25°C − 16 − ns TC = 25°C − 13 − n TC = 25°C − 43 − nC 5. Test pulse width = 300 ms, Duty Cycle = 2% Table 6. THERMAL RESISTANCE Parameters Min Typ Max Unit RθJC (per MOSFET chip) Q1,Q2 Thermal Resistance Junction−to−Case (Note 6) − 0.66 0.92 °C/W RθJS (per MOSFET chip) Q1,Q2 Thermal Resistance Junction−to−Sink (Note 7) − 1.20 − °C/W RθJC (per DIODE chip) D1,D2 Thermal Resistance Junction−to−Case (Note 6) − 1.98 2.72 °C/W RθJS (per DIODE chip) D1,D2 Thermal Resistance Junction−to−Sink (Note 7) − 2.97 − °C/W 6. Test method compliant with MIL STD 883−1012.1, from case temperature under the chip to case temperature measured below the package at the chip center, Cosmetic oxidation and discoloration on the DBC surface allowed 7. Defined by thermal simulation assuming the module is mounted on a 5 mm Al−360 die casting material with 30 um of 1.8 W/mK thermal interface material Table 7. ISOLATION (Isolation resistance at tested voltage between the base plate and to control pins or power terminals.) Test Test Conditions Isolation Resistance Unit Leakage @ Isolation Voltage (Hi−Pot) VAC = 5 kV, 60 Hz 100M < W www.onsemi.com 5 FAM65CR51DZ1, FAM65CR51DZ2 PARAMETER DEFINITIONS Reference to Table 3: Parameter of MOSFET Electrical Specifications BVDSS Q1, Q2 MOSFET Drain−to−Source Breakdown Voltage The maximum drain−to−source voltage the MOSFET can endure without the avalanche breakdown of the body− drain P−N junction in off state. The measurement conditions are to be found in Table 3. The typ. Temperature behavior is described in Figure 14 VGS(th) Q1, Q2 MOSFET Gate to Source Threshold Voltage The gate−to−source voltage measurement is triggered by a threshold ID current given in conditions at Table 4. The typ. Temperature behavior can be found in Figure 11 RDS(ON) Q1, Q2 MOSFET On Resistance RDS(on) is the total resistance between the source and the drain during the on state. The measurement conditions are to be found in Table 3. The typ behavior can be found in Figure 12 and Figure 13 as well as Figure 18 gFS Q1, Q2 MOSFET Forward Transconductance Transconductance is the gain in the MOSFET, expressed in the Equation below. It describes the change in drain current by the change in the gate−source bias voltage: gfs = [ DIDS / DVGS ]VDS IGSS Q1, Q2 MOSFET Gate−to−Source Leakage Current The current flowing from Gate to Source at the maximum allowed VGS The measurement conditions are described in the Table 3. IDSS Q1, Q2 MOSFET Drain−to−Source Leakage Current Drain – Source current is measured in off state while providing the maximum allowed drain−to-source voltage and the gate is shorted to the source. IDSS has a positive temperature coefficient. www.onsemi.com 6 FAM65CR51DZ1, FAM65CR51DZ2 Figure 3. Timing Measurement Variable Definition Table 8. PARAMETER OF SWITCHING CHARACTERISTICS Turn−On Delay (td(on)) This is the time needed to charge the input capacitance, Ciss, before the load current ID starts flowing. The measurement conditions are described in the Table 3. For signal definition please check Figure 3 above. Rise Time (tr) The rise time is the time to discharge output capacitance, Coss. After that time the MOSFET conducts the given load current ID. The measurement conditions are described in the Table 3. For signal definition please check Figure 3 above. Turn−On Time (ton) Is the sum of turn−on−delay and rise time Turn−Off Delay (td(off)) td(off) is the time to discharge Ciss after the MOSFET is turned off. During this time the load current ID is still flowing The measurement conditions are described in the Table 3. For signal definition please check Figure 3 above. Fall Time (tf) Turn−Off Time (toff) The fall time, tf, is the time to charge the output capacitance, Coss. During this time the load current drops down and the voltage VDS rises accordingly. The measurement conditions are described in the Table 3. For signal definition please check Figure 3 above. Is the sum of turn−off−delay and fall time www.onsemi.com 7 FAM65CR51DZ1, FAM65CR51DZ2 Figure 4. Dynamic Parameters of Silicon Diode (not in scale) Reference to Table 5: Parameter of Diode Electrical Specifications Instantaneous Reverse Current (IR) Current flowing in reverse after the reverse recovery time trr.. IR is shown in Figure 4 above The behaviour over voltage can be seen in Figure 23. Instantaneous Forward Voltage VFM Voltage drop over the diode in a dynamic condition given in Note 5. The voltage is measured after the given test pulse width. To avoid self heating effects a small duty cycle is used The behaviour over voltage can be seen in Figure 22. Reverse Recovery Time trr Time to reach peak reverse current ta During this transition time,from conduction to blocking, the current is flowing in reverse direction and diode generates switching losses. The time is characterized on the scope by using the ta and tb approximation method ta + tb = trr parameter result in Table 3 The parameter is dependent on temperature and initial dI/dt Figure 25 shows the dependency on dI/dt ta is the transition time from the moment the current starts to flow in reverse direction until the diode voltage drops (also the reverse current peak) Time from peak IRRM to zero crossing tb is defined by using a linear approximation from the peak IRM to a projected zero crossing of IR tb by crossing IR at 25% of IRRM Reverse Recovered Charge Qrr The reverse recovery charge is defined as Qrr = ∫ trr Ir(t) dt This parameter is highly depend on temperature and dI/dt See Figure 27. www.onsemi.com 8 FAM65CR51DZ1, FAM65CR51DZ2 TYPICAL CHARACTERISTICS − MOSFETs 40 0.6 0.4 RqJC = 0.92°C/W 0 ID, DRAIN CURRENT (A) 25 50 75 100 125 20 15 10 RqJC = 0.92°C/W 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (°C) TC, CASE TEMPERATURE (°C) Figure 5. Normalized Power Dissipation vs. Case Figure 6. Maximum Continuous ID vs. Case Temperature VDS = 20 V 40 TJ = 25°C 30 20 TJ = 150°C 10 TJ = −55°C 3 4 5 6 7 8 VGS = 0 V 100 10 TJ = 150°C 1 TJ = 25°C 0.1 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VGS, GATE−TO−SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Forward Diode 100 80 VGS = 15 V 70 10 V 90 8.0 V 60 50 7.0 V 40 30 6.0 V 20 5.5 V 10 0 25 0 150 50 0 30 5 IS, REVERSE DRAIN CURRENT (A) 0.2 60 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 0.8 0 VGS = 10 V 35 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 5.0 V 0 1 2 3 4 5 6 7 8 9 10 80 VGS = 15 V 70 10 V 60 8.0 V 50 7.0 V 40 30 6.0 V 20 5.5 V 10 0 5.0 V 0 10 20 30 40 50 60 70 80 90 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 9. On Region Characteristics (255C) Figure 10. On Region Characteristics (1505C) www.onsemi.com 9 FAM65CR51DZ1, FAM65CR51DZ2 TYPICAL CHARACTERISTICS − MOSFETs TJ = 150°C 100 TJ = 25°C 50 5.5 6.5 7.5 8.5 1.5 1.0 0.5 0 −75 −50 −25 0 25 50 75 100 125 150 175 VGS, GATE−TO−SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C) Figure 11. On−Resistance vs. Gate−to−Source Voltage Figure 12. RDS(norm) vs. Junction Temperature ID = 3.3 mA 1.0 0.8 0.6 −75 −50 −25 0 25 50 75 100 125 150 175 1.2 ID = 10 A 1.1 1.0 0.9 0.8 −75 −50 −25 0 25 50 75 100 125 150 175 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 13. Normalized Gate Threshold Voltage vs. Temperature Figure 14. Normalized Breakdown Voltage vs. Temperature 100K 30 25 CAPACITANCE (pF) 10K 20 Eoss (mJ) ID = 20 A VGS = 10 V 2.0 9.5 1.2 15 10 CISS 1K COSS 100 CRSS VGS = 0 V f = 1 MHz 10 5 0 2.5 RDS(ON), NORMALIZED DRAIN−TO− SOURCE ON−RESISTANCE 150 0 NORMALIZED GATE THRESHOLD VOLTAGE ID = 20 A NORMALIZED DRAIN−TO−SOURCE BREAKDOWN VOLTAGE RDS(ON), ON−RESISTANCE (mW) 200 0 100 200 300 400 500 600 700 1 0.1 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 15. Eoss vs. Drain−to−Source Voltage Figure 16. Capacitance Variation www.onsemi.com 10 1000 FAM65CR51DZ1, FAM65CR51DZ2 0.060 10 VDD = 130 V TC = 25°C RDS(on), DRAIN−TO−SOURCE ON RESISTANCE (W) VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS − MOSFETs 8 0.055 VDD = 400 V 6 VGS = 10 V 0.050 4 0.045 2 0 VGS = 20 V 0 40 80 120 0.040 160 0 20 40 ID, DRAIN CURRENT (A) Figure 17. Gate Charge Characteristics Figure 18. ON−Resistance Variation with Drain Current and Gage Voltage For temperatures above 25°C derate peak current as follows: 100 ZqJA, NORMALIZED THERMAL IMPEDANCE (°C/W) IDM, PEAK CURRENT (A) ID, DRAIN CURRENT (A) VGS = 10 V 10 TC = 25°C Single Pulse RqJC = 0.92°C/W RDS(on) Limit Thermal Limit Package Limit 1 10 1 ms 10 ms 100 ms 1s 100 I + I 25 1000 100 ms 0.1 80 QG, GATE CHARGE (nC) 10,000 1 60 1000 Ǹ 150 * T C 125 TC = 25°C 100 Limited IDM 206 A Single Pulse 10 0.000001 0.00001 0.0001 NOTES: RqJC = 0.92°C/W Duty Cycle, D = t1/t2 Peak TJ = PDM x ZqJC(t) + TC 0.001 0.01 0.1 VDS, DRAIN−TO−SOURCE VOLTAGE (V) t, PULSE WIDTH (sec) Figure 19. Safe Operating Area Figure 20. Peak Current Capability 1 10 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 Single Pulse 0.001 0.00001 0.0001 0.001 0.1 0.01 t, RECTANGULAR PULSE DURATION (sec) Figure 21. Transient Thermal Impedance www.onsemi.com 11 1 10 100 FAM65CR51DZ1, FAM65CR51DZ2 TYPICAL CHARACTERISTICS − DIODES 1000 IR, REVERSE CURRENT (mA) TA = 100°C TA = 125°C TA = 25°C 10 1 0.2 0.7 1.2 1.7 2.2 2.7 1 0.1 25°C 0.01 300 400 500 Figure 22. Typical Forward Voltage Drop vs. Forward Current Figure 23. Typical Reverse Current vs. Reverse Voltage 300 200 100 0.1 1 10 100 50 25°C 0 100 200 300 400 Figure 24. Capacitance Figure 25. Reverse Recovery Time vs. di/dt 10 25°C 5 100 125°C 100 di/dt (A/ms) 125°C 200 300 400 500 600 150 VR, REVERSE VOLTAGE (V) 15 0 200 VR, REVERSE VOLTAGE (V) 400 0 100 VF, FORWARD VOLTAGE (V) trr, REVERSE RECOVERY TIME (ns) C, CAPACITANCE (pF) 125°C 10 0.0001 3.2 500 Irr, REVERSE RECOVERY CURRENT (A) 100 0.001 Qrr, REVERSE RECOVERY CHARGE (nC) IF, FORWARD CURRENT (A) 100 500 500 400 125°C 300 200 25°C 100 0 100 200 300 400 500 di/dt (A/ms) di/dt (A/ms) Figure 26. Reverse Recovery Current vs. di/dt Figure 27. Reverse Recovery Charge vs. di/dt www.onsemi.com 12 FAM65CR51DZ1, FAM65CR51DZ2 ZqJC, NORMALIZED THERMAL IMPEDANCE (°C/W) TYPICAL CHARACTERISTICS − DIODES 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 Single Pulse 0.001 0.00001 0.001 0.1 t, RECTANGULAR PULSE DURATION (sec) Figure 28. Transient Thermal Impedance www.onsemi.com 13 10 1000 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS APMCD−A16 / 12LD, AUTOMOTIVE MODULE CASE MODGG ISSUE C GENERIC MARKING DIAGRAM* XXXXXXXXXXXXXXXX ZZZ ATYWW NNNNNNN DOCUMENT NUMBER: DESCRIPTION: XXXX ZZZ AT Y WW NNN 98AON94738G = Specific Device Code = Lot ID = Assembly & Test Location = Year = Work Week = Serial Number DATE 03 NOV 2021 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. APMCD−A16 / 12LD, AUTOMOTIVE MODULE PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS APMCD−B16 / 12LD, AUTOMOTIVE MODULE CASE MODGK ISSUE D GENERIC MARKING DIAGRAM* XXXXXXXXXXXXXXXX ZZZ ATYWW NNNNNNN DOCUMENT NUMBER: DESCRIPTION: XXXX ZZZ AT Y W NNN 98AON97134G = Specific Device Code = Lot ID = Assembly & Test Location = Year = Work Week = Serial Number DATE 04 NOV 2021 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. APMCD−B16 / 12LD, AUTOMOTIVE MODULE PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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