FAN2365MPX

FAN2365 TinyBuck™ 15 A Integrated Synchronous Buck Regulator Features Description     VIN Range: 4.5 V to 24 V The FAN2365 TinyBuck™ is a highly efficient integrated synchronous buck regulator. The regulator is capable of operating with an input range from 4.5 V to 24 V and supporting up to 15 A continuous load currents.            PFM Mode for Light-Load Efficiency High Efficiency: Over to 96% Peak Continuous Output Current: 15 A MOSFETs RDS,ON (Typical): HS: 6.46 mΩ, LS: 1.58 mΩ Excellent Line and Load Transient Response Precision Reference: ±1% Over Temperature Output Voltage Range: 0.6 to 5.5 V Programmable Frequency: 200 kHz to 1 MHz Programmable Soft-Start Low Shutdown Current Adjustable Sourcing Current Limit Internal Boot Diode Thermal Shutdown The FAN2365 utilizes Fairchild’s constant on-time control architecture to provide excellent transient response and to maintain a relatively constant switching frequency. This device utilizes Pulse Frequency Modulation (PFM) mode to maximize light-load efficiency by reducing switching frequency when the inductor is operating in discontinuous conduction mode at light loads, while clamping the minimum frequency above the audible range with ultrasonic mode. Switching frequency and over-current protection can be programmed to provide a flexible solution for various applications. Output over-voltage, undervoltage, over-current, and thermal shutdown protections help prevent damage to the device during fault conditions. After thermal shutdown is activated, a hysteresis feature restarts the device when normal operating temperature is reached. Halogen and Lead Free, RoHS Compliant Applications       Mainstream Notebooks Servers and Desktop Computers Game Consoles Telecommunications Storage Base Stations Ordering Information Part Number Configuration Operating Temperature Range Output Current (A) FAN2365MPX PFM with Ultrasonic Mode -40 to 125°C 15 Package 34-Lead, PQFN, 5.5 mm x 5.0 mm Forced PWM or no ultrasonic mode available on request. Please address support questions to "tinybucksupport@fairchildsemi.com". © 2011 Fairchild Semiconductor Corporation FAN2365 • Rev. 1.0.5 www.fairchildsemi.com FAN23SV06 / FAN23SV06P — TinyBuck™ 6 A Integrated Synchronous Buck Regulator May 2014 VBIAS = 5V R11 10Ω C9 0.1µF C10 2.2µF PVCC VCC Ext EN VIN = 19V CIN 0.1µF VIN CIN 4x10µF PVIN C3 0.1µF EN VOUT = 1.2V IOUT=0-15A BOOT L1 0.56µH FAN2365 SW PGOOD ILIM SOFT START R2 1.5kΩ R5 1.47kΩ C7 15nF C4 0.1µF C5 100pF FREQ R3 10kΩ FB R9 54.9kΩ AGND R4 10kΩ PGND Figure 1. Typical Application Functional Block Diagram VIN BOOT PVIN PVCC PVCC VCC VCC VCC UVLO 0.8V/ 2.0V COUT 8x47µF FAN2365 — TinyBuck™ 15 A Integrated Synchronous Buck Regulator Typical Application Diagram PVCC EN ENABLE VCC VCC 10µA Modulator HS Gate Driver SS FB FB Comparator VREF SW FREQ Control Logic x1.2 2nd Level Over Voltage Comparator x1.1 1st Level Over Voltage Comparator x0.9 Under Voltage Comparator PFM Comparator PVCC LS Gate Driver VCC PGOOD Thermal Shutdown 10µA Current Limit Comparator AGND ILIM Figure 2. © 2011 Fairchild Semiconductor Corporation FAN2365 • Rev. 1.0.5 PGND Block Diagram www.fairchildsemi.com 2 9 VIN 9 SW PVIN PVIN 8 BOOT PVIN 7 AGND PVIN 6 PVIN PVIN 5 PVIN AGND 4 PVIN BOOT 3 PVIN SW 2 PVIN VIN 1 8 7 6 5 4 3 2 1 10 PVIN PVIN 10 34 NC 11 PVIN PVIN 11 33 NC 12 SW SW 12 32 FREQ 13 SW SW 13 31 SS 14 SW SW 30 PGOOD 29 15 SW SW 15 29 EN NC 28 16 SW SW 16 28 NC FB 27 17 SW SW 17 27 FB 24 23 22 21 20 PVCC ILIM AGND SW PGND PGND 19 18 Figure 3. Pin Assignments, Bottom View 18 19 20 21 22 23 24 25 26 VCC 26 25 VCC EN 14 PVCC SW (P3) PGOOD 30 ILIM AGND (P1) AGND 31 SW SS PGND 32 PGND FREQ PGND 33 PGND NC PVIN (P2) PGND 34 PGND NC Figure 4. Pin Assignments, Top View Pin Definitions Name Pad / Pin PVIN P2, 5-11 VIN 1 Input to the modulator for input voltage feed-forward PVCC 25 Power supply input for the low-side gate driver and boot diode VCC 26 Power supply input for the controller PGND 18-21 AGND P1, 4, 23 SW Description Power input for the power stage Power ground for the low-side power MOSFET and for the low-side gate driver Analog ground for the analog portions of the IC and for substrate P3, 2, 12-17, 22 Switching node; junction between high-and low-side MOSFETs BOOT 3 Supply for high-side MOSFET gate driver. A capacitor from BOOT to SW supplies the charge to turn on the N-channel high-side MOSFET. During the freewheeling interval (low-side MOSFET on), the high-side capacitor is recharged by an internal diode connected to PVCC. ILIM 24 Current limit. A resistor between ILIM and SW sets the current limit threshold. FB 27 Output voltage feedback to the modulator EN 29 Enable input to the IC. Pin must be driven logic high to enable, or logic low to disable. SS 31 Soft-start input to the modulator FREQ 32 On-time and frequency programming pin. Connect a resistor between FREQ and AGND to program on-time and switching frequency. PGOOD 30 Power good; open-drain output indicating VOUT is within set limits. NC 28, 33-34 Leave pin open or connect to AGND. © 2011 Fairchild Semiconductor Corporation FAN2365 • Rev. 1.0.5 www.fairchildsemi.com 3 FAN2365 — TinyBuck™ 15 A Integrated Synchronous Buck Regulator Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VPVIN VIN VBOOT VSW Parameter Conditions Min. Max. Unit Power Input Referenced to PGND -0.3 30.0 V Modulator Input Referenced to AGND -0.3 30.0 V Referenced to PVCC -0.3 30.0 V Referenced to PVCC, ∆𝑉𝐹𝐵 (8) where ∆IIND is the inductor current ripple and ∆VFB is the ripple voltage on VFB, which should be ≥12 mV. In certain applications, especially designs utilizing only ceramic output capacitors, there may not be sufficient ripple magnitude available on the feedback pin for stable operation. In this case, an external circuit can be added to inject ripple voltage into the FB pin. There are some specific considerations when selecting the RCC ripple injector circuit. For typical applications, the value of C4 can be selected as 0.1 µF and approximate values for R2 and C5 can be determined using the following equations. R2 must be small enough to develop 12 mV of ripple: 𝑅2 < (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 ) ∙ 𝑉𝑂𝑈𝑇 𝑉𝐼𝑁 ∙ 0.012𝑉 ∙ 𝐶4 ∙ 𝑓𝑆𝑊 (9) R2 must be selected such that the R2C4 time constant enables stable operation: 0.33 ∙ 2𝜋 ∙ 𝑓𝑆𝑊 ∙ 𝐿𝑂𝑈𝑇 ∙ 𝐶𝑂𝑈𝑇 (10) 𝑅2 < 𝐶4 The minimum value of C5 can be selected to minimize the capacitive component of ripple appearing on the feedback pin: LOUT ∙ COUT ∙ (R3 + R4) (11) R2 ∙ R3 ∙ R4 ∙ C4 Using the minimum value of C5 generally offers the best transient response, and 100pF is a good initial value in many applications. However, under some operating conditions excessive pulse jitter may be observed. To reduce jitter and improve stability, the value of C5 can be increased: C5MIN > 𝐶5 ≥ 2 ∙ C5MIN (12) 5 V PVCC The PVCC is supplied from an external source to provide power to the drivers and VCC. It is crucial to keep this pin decoupled to PGND with a≥ 1 µF X5R or X7R ceramic capacitor. Because VCC powers internal analog circuit, it is filtered from PVCC with a 10 Ω resistor and 0.1 µF X7R decoupling ceramic capacitor to AGND. Setting the Output Voltage (VOUT) The output voltage VOUT is regulated by initiating a highside MOSFET on-time interval when the valley of the © 2011 Fairchild Semiconductor Corporation FAN2365 • Rev. 1.0.5 divided output voltage appearing at the FB pin reaches VREF. Since this method regulates at the valley of the output ripple voltage, the actual DC output voltage on VOUT is offset from the programmed output voltage by the average value of the output ripple voltage. The initial VOUT setting of the regulator can be programmed from 0.6 V to 5.5 V by an external resistor divider (R3 and R4): 𝑅4 = 𝑅3 𝑉𝑂𝑈𝑇 � �−1 𝑉𝑅𝐸𝐹 (13) where VREF is 600 mV. For example; for 1.2 V VOUT and 10 kΩ R3, then R4 is 10 kΩ. For 600 mV VOUT, R4 is left open. VFB is trimmed to a value of 596 mV when VREF=600 mV, so the final output voltage, including the effect of the output ripple voltage, can be approximated by the equation: 𝑉𝑂𝑈𝑇 = 𝑉𝐹𝐵 ∗ �1 + 𝑉𝑟𝑖𝑝 𝑅3 �+� � 𝑅4 2 (14) Setting the Switching Frequency (fSW) fSW is programmed through external RFREQ as follows: 𝑅𝐹𝑅𝐸𝑄 = 𝑉𝑂𝑈𝑇 20 ∗ 𝐶𝑡𝑂𝑁 ∗ 𝑓𝑆𝑊 (15) where CtON=2.2 pF internal capacitor that generates tON. For example; for fSW=500 kHz and VOUT=1.2 V, select a standard value for RFREQ=54.9 kΩ. Inductor Selection The inductor is typically selected based on the ripple current (∆IL), which is approximately 25% to 45% of the maximum DC load. The inductor current rating should be selected such that the saturation and heating current ratings exceed the intended currents encountered in the application over the expected temperature range of operation. Regulators that require fast transient response use smaller inductance and higher current ripple; while regulators that require higher efficiency keep ripple current on the low side. The inductor value is given by: 𝐿= (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 ) 𝑉𝑂𝑈𝑇 ∙ ∆𝐼𝐿 ∙ 𝑓𝑆𝑊 𝑉𝐼𝑁 (16) For example: for 19 V VIN, 1.2 V VOUT, 15 A load, 25% ∆IL, and 500 kHz fSW; L is 576 nH, and a standard value of 560 nH is selected. Input Capacitor Selection Input capacitor CIN is selected based on voltage rating, RMS current ICIN(RMS) rating, and capacitance. For capacitors having DC voltage bias derating, such as ceramic capacitors, higher rating is strongly recommended. RMS current rating is given by: 𝐼𝐶𝐼𝑁(𝑅𝑀𝑆) = 𝐼𝐿𝑂𝐴𝐷−𝑀𝐴𝑋 ∙ �𝐷 ∙ (1 − 𝐷) 13 (17) www.fairchildsemi.com FAN2365 -— TinyBuck™ 15 A Integrated Synchronous Buck Regulator Application Information approximately 20 µA is output onto the ILIM pin, which creates a voltage across the resistor. When the voltage on ILIM goes negative, an over-current condition is detected. The capacitance is given by: 𝐶𝐼𝑁 𝐼𝐿𝑂𝐴𝐷−𝑀𝐴𝑋 ∙ 𝐷 ∙ (1 − 𝐷) = 𝑓𝑆𝑊 ∙ ∆𝑉𝐼𝑁 The current flowing out of the ILIM pin through RILIM is trimmed to compensate for both the RDS(ON) of the LS MOSFET and the offset voltage of the current limit comparator. RILIM is calculated by: (18) where ∆VIN is the input voltage ripple, normally 1% of VIN. 𝑅𝐼𝐿𝐼𝑀 = 1.08 ∙ 𝐾𝐼𝐿𝐼𝑀 ∙ 𝐼𝐼𝐿𝐼𝑀,𝑉𝐴𝐿𝐿𝐸𝑌 For example; for VIN=19 V, ∆VIN=120 mV, VOUT=1.2 V, 15 A load, and fSW=500 kHz; CIN is 14.8 µF and ICIN(RMS) is 3.64 ARMS. Select a minimum of three 10 µF 25 Vrated ceramic capacitors with X7R or similar dielectric, recognizing that the capacitor DC bias characteristic indicates that the capacitance value falls approximately 60% at VIN=19 V, with a resultant small increase in ∆VIN ripple voltage above 120 mV used in the calculation. Also, each 10 µF can carry over 3 ARMS in the frequency range from 100 kHz to 1 MHz, exceeding the input capacitor current rating requirements. An additional 0.1 µF capacitor may be needed to suppress noise generated by high frequency switching transitions. With the constant on-time architecture, HS is always turned on for a fixed on-time; this determines the peakto-peak inductor current. Current ripple ∆I is given by: Output Capacitor Selection ∆𝐼𝐿 = Output capacitor COUT is selected based on voltage rating, RMS current ICOUT(RMS) rating, and capacitance. For capacitors having DC voltage bias derating, such as ceramic capacitors, higher rating is highly recommended. 2 2 𝐼𝑀𝐴𝑋 − 𝐼𝑀𝐼𝑁 2 (𝑉𝑂𝑈𝑇 + ∆𝑉𝑂𝑈𝑇 )2 − 𝑉𝑂𝑈𝑇 (21) The FAN2365 uses valley-current sensing, the current limit (IILIM) set point is the valley (IVALLEY). The valley current level for calculating RILIM is given by: 𝐼𝑉𝐴𝐿𝐿𝐸𝑌 = 𝐼𝐿𝑂𝐴𝐷 (𝐶𝐿) − ∆𝐼𝐿 2 (22) where ILOAD (CL) is the DC load current when the current limit threshold is reached.. (19) For example: In a converter designed for 15 A steadystate operation and 4.5 A current ripple, the current-limit threshold could be selected at 120% of ILOAD,(MAX) to accommodate transient operation and inductor value decrease under loading. As a result, ILOAD,(MAX) is 18 A, IVALLEY=15.75 A, and RILIM is selected as the standard value of 1.47 kΩ. where IMAX and IMIN are maximum and minimum load steps, respectively and ∆VOUT is the voltage overshoot, usually specified at 3 to 5%. For example: for VI=19 V, VOUT=1.2 V, 10 A IMAX, 5 A IMIN, fSW=500 kHz, LOUT=560 nH, and 3% ∆VOUT ripple of 36 mV; the COUT value is calculated to be 360 µF. This capacitor requirement can be satisfied using eight 47 µF, 6.3 V-rated X5R ceramic capacitors. This calculation applies for load current slew rates that are faster than the inductor current slew rate, which can be defined as VOUT/L during the load current removal. Boot Resistor In some applications, especially with higher input voltage, the VSW ring voltage may exceed derating guidelines of 80% to 90% of absolute rating for VSW . In this situation a resistor can be connected in series with boot capacitor (C3 in Figure 1) to reduce the turn-on speed of the high side MOSFET to reduce the amplitude of the VSW ring voltage. If necessary, a resistor and capacitor snubber can be added from VSW to PGND to reduce the magnitude of the ringing voltage. Please contact tinybucksupport@fairchildsemi.com for assistance selecting a boot resistor or snubber circuit in applications that operate above a 21 V typical input voltage. Setting the Current Limit Current limit is implemented by sensing the inductor valley current across the LS RDS(ON) during the LS ontime. The current limit comparator prevents a new ontime from being started until the valley current is less than the current limit. The set point is configured by connecting a resistor from the ILIM pin to the SW pin. A trimmed current of © 2011 Fairchild Semiconductor Corporation FAN2365 • Rev. 1.0.5 (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 ) ∗ 𝑡𝑂𝑁 𝐿 From the equation above, the worst-case ripple occurs during an output short circuit (where VOUT is 0 V). This should be taken into account when selecting the current limit set point. When calculating COUT, usually the dominant requirement is the current load step transient. If the unloading transient requirement (IOUT transitioning from HIGH to LOW), is satisfied, then the load transient (IOUT transitioning LOW to HIGH), is also usually satisfied. The unloading COUT calculation, assuming COUT has negligible parasitic resistance and inductance in the circuit path, is given by: 𝐶𝑂𝑈𝑇 = 𝐿 ∙ (20) where KILIM is the current source scale factor equal to the average RDS,ON of the LS MOSFET divided by the average ILIM pin current of 20 µA, and IVALLEY is the inductor valley current when the current limit threshold is reached. The factor 1.08 accounts for the temperature offset of the LS MOSFET compared to control circuit (approximately 20°C), and the approximate increase in the RDS,on of the LS MOSFET of 4000 ppm/°C. www.fairchildsemi.com 14 FAN2365 — TinyBuck™ 15 A Integrated Synchronous Buck Regulator where ILOAD-MAX is the maximum load current and D is the duty cycle VOUT/VIN. The maximum ICIN(RMS) occurs at 50% duty cycle. The following points should be considered before beginning a PCB layout using the FAN2365. A sample PCB layout from the TinyBuck™ evaluation board is shown in Figure 28-Figure 31 following the layout guidelines. The current return path from PGND at the low-side MOSFET source to the negative terminal of the input capacitor can be routed under the inductor and also through vias that connect the input capacitor and lowside MOSFET source to the PGND region under the power portion of the IC. Power components consisting of the input capacitors, output capacitors, inductor, and TinyBuck™ device should be placed on a common side of the pcb in close proximity to each other and connected using surface copper. The SW node trace which connects the source of the high-side MOSFET and the drain of the low-side MOSFET to the inductor should be short and wide. Sensitive analog components including SS, FB, ILIM, FREQ, and EN should be placed away from the highvoltage switching circuits such as SW and BOOT, and connected to their respective pins with short traces. To control the voltage across the output capacitor, the output voltage divider should be located close to the FB pin, with the upper FB voltage divider resistor connected to the positive side of the output capacitor, and the bottom resistor should be connected to the AGND portion of the TinyBuck™ device. The inner PCB layer closest to the TinyBuck™ device should have Power Ground (PGND) under the power processing portion of the device (PVIN, SW, and PGND). This inner PCB layer should have a separate Analog Ground (AGND) under the P1 pad and the associated analog components. AGND and PGND should be connected together near the IC between PGND pins 18-21 and AGND pin 23 which connects to P1 thermal pad. When using ceramic capacitor solutions with external ramp injection circuitry (R2, C4, C5 in Figure 1), R2 and C4 should be connected near the inductor, and coupling capacitor C5 should be placed near FB pin to minimize FB pin trace length. Decoupling capacitors for PVCC and VCC should be located close to their respective device pins. The AGND thermal pad (P1) should be connected to AGND plane on inner layer using four 0.25 mm vias spread under the pad. No vias are included under PVIN (P2) and SW (P3) to maintain the PGND plane under the power circuitry intact. SW node connections to BOOT, ILIM, and ripple injection resistor R2 should be made through separate traces. Power circuit loops that carry high currents should be arranged to minimize the loop area. Primary focus © 2011 Fairchild Semiconductor Corporation FAN2365 • Rev. 1.0.5 www.fairchildsemi.com 15 FAN2365 — TinyBuck™ 15 A Integrated Synchronous Buck Regulator should be directed to minimize the loop for current flow from the input capacitor to PVIN, through the internal MOSFETs, and returning to the input capacitor. The input capacitor should be placed as close to the PVIN terminals as possible. Printed Circuit Board (PCB) Layout Guidelines Figure 29. © 2011 Fairchild Semiconductor Corporation FAN2365 • Rev. 1.0.5 FAN2365 — TinyBuck™ 15 A Integrated Synchronous Buck Regulator Figure 28. Evaluation Board Top Layer Copper Evaluation Board Inner Layer 1 Copper www.fairchildsemi.com 16 Evaluation Board Inner Layer 2 Copper Figure 31. Evaluation Board Bottom Layer Copper FAN2365 — TinyBuck™ 15 A Integrated Synchronous Buck Regulator © 2011 Fairchild Semiconductor Corporation FAN2365 • Rev. 1.0.5 Figure 30. www.fairchildsemi.com 17 FAN2365 — TinyBuck™ 15 A Integrated Synchronous Buck Regulator Physical Dimensions 5.50±0.10 26 18 1.05±0.10 17 27 0.25±0.05 (30X) 5.00±0.10 34 0.25±0.05 0.025±0.025 10 9 1 TOP VIEW PIN#1 INDICATOR SEATING PLANE DETAIL 'A' SEE DETAIL 'A' SCALE: 2:1 FRONT VIEW 1.58±0.01 (0.35) 2.18±0.01 (0.43) 0.50±0.01 9 1 (0.25) 0.40±0.01 (30X) (0.35) 34 10 0.68±0.01 (0.35) 3.50±0.01 2.58±0.01 (1.75) 17 (0.75) (0.33) (0.35) 27 0.43±0.01 18 26 (0.25) (0.35) NOTES: UNLESS OTHERWISE SPECIFIED A) NO INDUSTRY REGISTRATION APPLIES. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E) DRAWING FILE NAME: MKT-PQFN34AREV2 F) FAIRCHILD SEMICONDUCTOR Figure 32. (0.28) (3X) (0.24) 1.75±0.01 BOTTOM VIEW 34-Lead, PQFN, 5.5 mm x 5.0 mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/PQ/PQFN34A.pdf For current packing container specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packing_dwg/PKG-PQFN34A.pdf © 2011 Fairchild Semiconductor Corporation FAN2365 • Rev. 1.0.5 www.fairchildsemi.com 18 FAN2365 -— TinyBuck™ 15 A Integrated Synchronous Buck Regulator © 2011 Fairchild Semiconductor Corporation FAN2365 • Rev. 1.0.5 19 www.fairchildsemi.com