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FAN23SV04T
4 A Synchronous Buck Regulator for DDR Termination
Features
Description
VIN Range: 7 V to 18 V Using Internal Linear
Regulator for Bias
VIN Range: 4.5 V to 5.5 V with VIN/PVIN/PVCC
Connected to Bypass Internal Regulator
High Efficiency
The FAN23SV04T is a highly efficient, synchronous
buck regulator for use in tracking applications, such as
DDR termination rails. The V DDQ input includes an
internal 2:1 resistive voltage divider to reduce total
circuit size and component count. The regulator
operates with an input range from 7 V to 18 V and
supports up to 4 A load currents. The device can
operate from a 5 V rail (±10%) if VIN, PVIN, and PVCC
are connected together to bypass the internal linear
regulator.
Continuous Output Current: 4 A
Internal Linear Bias Regulator
Internal VDDQ Resistor Divider
This device utilizes Fairchild’s constant on-time control
architecture to provide excellent transient response and
to maintain a relatively constant switching frequency.
Excellent Line and Load Transient Response
Output Voltage Range: 0.5 to 1.5 V
Programmable Frequency: 200 kHz to 1.5 MHz
Programmable Soft-Start
Low Shutdown Current
Switching frequency and sourcing over-current
protection can be programmed to provide a flexible
solution for various applications.
Output over-current, and thermal shutdown protections
help prevent damage during fault conditions. A
hysteresis feature restarts the device when normal
operating temperature is reached.
Adjustable Sourcing Current Limit
Internal Boot Diode
Thermal Shutdown
Halogen and Lead Free, RoHS Compliant
Applications
Bus Termination
Servers and Desktop Computers
NVDC Notebooks, Netbooks
Game Consoles
Ordering Information
Part Number
Configuration
Operating
Temperature Range
Output
Current
Package
FAN23SV04TMPX
PWM Mode with
VDDQ Tracking Input
-40 to 125°C
4A
34-Lead, PQFN, 5.5 mm x 5.0 mm
© 2011 Fairchild Semiconductor Corporation
FAN23SV04T • Rev. 1.13
www.fairchildsemi.com
FAN23SV04T — 4 A Synchronous Buck Regulator for DDR Termination
September 2015
VIN=12V
C3
0.1µF
L1
1µH
11
15 SW
16
SW
17
SW
R3
10k
SW
BOOT
PVIN
AGND
VIN
VDDQ
SS
EN
NC
FB
VCC
PVCC
ILIM
AGND
C5
470pF
R8
10k
NC
FAN23SV04T
SW
R2
1k
R7
61.9k
1
FREQ
PGND
C4
0.1µF
2
NC
PGND
C10a
47µF
3
PVIN
PGND
C10b
47µF
4
12
PGND
C10d
47µF
5
PVIN
SW
13 SW
14 SW
C10d
47µF
6
PVIN
10
7
PVIN
PVIN
VOUT=0.6V
8
PVIN
9
C2
10µF
34
33
32
VDDQ
31
30
R9
27.4k
29
28
27
C7
15nF
18 19 20 21 22 23 24 25 26
R11
10
C9
2.2µF
C10
0.1µF
R5
1.02k
Figure 1. Typical Application with VIN = 12 V
VIN=5V
C3
0.1µF
15 SW
16
SW
17
SW
R3
10k
VIN
BOOT
AGND
PVIN
PVIN
SW
VDDQ
FAN23SV04T
SS
EN
NC
FB
VCC
C5
100pF
NC
PVCC
R2
1k
1
FREQ
ILIM
C4
0.1µF
2
SW
AGND
C10a
47µF
3
NC
PGND
C10b
47µF
4
PVIN
PGND
C10d
47µF
PVIN
PVIN
13 SW
14 SW
C10d
47µF
5
SW
12
6
PGND
11
7
PGND
10
L1
0.72µH
PVIN
VOUT=0.6V
8
PVIN
9
C2
10µF
34
33
32
VDDQ
31
30
EN
29
28
R9
C7 26.1k
15nF
27
18 19 20 21 22 23 24 25 26
R11
10
R5 1.1k
C10
0.1µF
C9
2.2µF
Figure 2. Typical Application with VIN = 5 V
© 2011 Fairchild Semiconductor Corporation
FAN23SV04T • Rev. 1.13
www.fairchildsemi.com
2
FAN23SV04T — 4 A Synchronous Buck Regulator for DDR Termination
Typical Application Diagrams
VIN
BOOT
PVIN
PVCC
Linear
Regulator
PVCC
VCC
VCC
VCC UVLO
EN
PVCC
ENABLE
VCC
Modulator
FB
HS Gate
Driver
SS
FB
Comparator
VDDQ
SW
FREQ
Thermal
Shutdown
VCC
Control
Logic
PVCC
20µA
LS Gate
Driver
ILIM
Current Limit
Comparator
AGND
PGND
Figure 3. Block Diagram
© 2011 Fairchild Semiconductor Corporation
FAN23SV04T • Rev. 1.13
www.fairchildsemi.com
3
FAN23SV04T — 4 A Synchronous Buck Regulator for DDR Termination
Functional Block Diagram
VIN
PVIN
9
SW
PVIN
8
BOOT
PVIN
7
AGND
PVIN
6
PVIN
PVIN
5
PVIN
AGND
4
PVIN
BOOT
3
PVIN
SW
2
PVIN
VIN
1
9
8
7
6
5
4
3
2
1
SW
12
32
13
SW
SW 13
31
VDDQ
14
SW
SW
14
30
SS
29
15
SW
SW 15
29
EN
NC
28
16
SW
SW 16
28
NC
FB
27
17
SW
SW 17
27
FB
PGND
19
PGND
22
18
PGND
23
18
PGND
24
19
PGND
25
20
PGND
26
21
SW
EN
SW
(P3)
AGND
30
ILIM
SS
AGND
(P1)
PVCC
31
VCC
VDDQ
Figure 4. Bottom View
20
21
22
23
24
25
26
VCC
SW
32
PVCC
12
FREQ
ILIM
PVIN 11
33
AGND
PVIN
NC
PVIN
(P2)
SW
11
34
PGND
PVIN
NC
PGND
10
PVIN 10
34
NC
33
NC
FREQ
Figure 5. Top View
Pin Definitions
Name
Pad / Pin
PVIN
P2; 5-11
VIN
1
Power input to the linear regulator; used in the modulator for input voltage feed-forward.
PVCC
25
Power output of the linear regulator; directly supplies power for the low-side gate driver
and boot diode. Can be connected to VIN and PVIN for operation from 5 V rail.
VCC
26
Power supply input for the controller.
PGND
18-21
AGND
P1; 4, 23
SW
Description
Power input for the power stage.
Power ground for the low-side power MOSFET and for the low-side gate driver.
Analog ground for the analog portions of the IC and for substrate.
P3; 2, 12-17, 22 Switching node; junction between high-and low-side MOSFETs.
BOOT
3
Supply for high-side MOSFET gate driver. A capacitor from BOOT to SW supplies the
charge to turn on the N-channel high-side MOSFET. During the freewheeling interval
(low-side MOSFET on), the high-side capacitor is recharged by an internal diode
connected to PVCC.
ILIM
24
Current limit. A resistor between ILIM and SW sets the current-limit threshold.
FB
27
Output voltage feedback to the modulator.
EN
29
Enable input to the IC. Pin must be driven logic high to enable, or logic low to disable.
SS
30
Soft-Start input to the modulator
VDDQ
31
External reference input to the modulator. The modulator regulates to half of the voltage
at the VDDQ pin.
FREQ
32
On-time and frequency programming pin. Connect a resistor between FREQ and AGND
to program on-time and switching frequency.
NC
28, 33-34
Leave pin open or connect to AGND.
© 2011 Fairchild Semiconductor Corporation
FAN23SV04T • Rev. 1.13
www.fairchildsemi.com
4
FAN23SV04T — 4 A Synchronous Buck Regulator for DDR Termination
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VPVIN
VIN
VBOOT
VSW
Parameter
Condition
Min.
Max.
Unit
Power Input
Referenced to PGND
-0.3
25.0
V
Modulator Input
Referenced to AGND
-0.3
25.0
V
Referenced to PVCC
-0.3
26.0
V
Referenced to PVCC, 5.5V a
series resistor is required to limit the current flow into
the EN pin clamp to less than 24 µA to keep the internal
clamp within normal operating range. The resistor value
can be calculated from the following equation:
This pin is connected to the VDDQ supply, which the
FAN23SV04T must track during startup and produce an
output (VTT) equal to half of VDDQ in steady-state
conditions. To accomplish this, the VDDQ pin has an
internal resistor divider to AGND that provides a
reference voltage equal to VDDQ/2 at the positive input of
the FB comparator.
(2)
Soft-Start (SS)
A conventional soft-start ramp is implemented to provide
a controlled startup sequence of the output voltage. A
current is generated on the SS pin to charge an external
capacitor. The lesser of the voltage on the SS pin and
the reference voltage is used for output regulation.
Constant On-Time Modulation
The FAN23SV04T uses a constant on-time modulation
technique, in which the HS MOSFET is turned on for a
fixed time, set by the modulator, in response to the input
© 2011 Fairchild Semiconductor Corporation
FAN23SV04T • Rev. 1.13
www.fairchildsemi.com
11
FAN23SV04T — 4 A Synchronous Buck Regulator for DDR Termination
Circuit Operation
Application Information
Stability
Constant on-time stability consists of two parameters:
stability criterion and sufficient signal at VFB.
Stability criterion is given by:
The nominal startup time is programmable through an
internal current source charging the external soft-start
capacitor CSS:
(8)
Sufficient signal requirement is given by:
(7)
(9)
where:
where IIND is the inductor current ripple and VFB is
the ripple voltage on VFB, which should be ≥12 mV.
CSS = External soft-start programming capacitor;
ISS
= Internal soft-start charging current source,
10 A;
tSS
= Soft-start time; and
In certain applications, especially designs utilizing only
ceramic output capacitors, there may not be sufficient
ripple magnitude available on the feedback pin for
stable operation. In this case, an external circuit, such
as R2-C4-C5 shown in Figure 1, can be added to inject
ripple voltage into the FB pin.
VREF = VDDQ/2.
For example; for 1 ms startup time, CSS=15 nF.
The soft-start option can be used for ratiometric tracking.
When EN is LOW, the soft-start capacitor is discharged.
There are some specific considerations when selecting
the RCC ripple injector circuit. For typical applications,
the value of C4 can be selected as 0.1 µF and
approximate values for R2 and C5 can be determined
using the following equations.
Internal Linear Regulator
The FAN23SV04T includes a linear regulator to facilitate
single-supply operation for self-biased applications.
PVCC is the linear regulator output and supplies power
to the internal gate drivers. The PVCC pin should be
bypassed with a 2.2 µF ceramic capacitor. The device
can operate from a 5 V rail if the V IN, PVIN, and PVCC
pins are connected together to bypass the internal
linear regulator.
R2 must be small enough to develop 12 mV of ripple:
(10)
R2 must also be selected such that the R2C4 time
constant enables stable operation:
VCC Bias Supply and UVLO
(11)
The VCC rail supplies power to the controller. It is
generally connected to the PVCC rail through a lowpass filter of a 10 resistor and 0.1 µF capacitor to
minimize any noise sources from the driver supply.
The minimum value of C5 can be selected to minimize
the capacitive component of ripple appearing on the
feedback pin:
An Under-Voltage Lockout (UVLO) circuit monitors the
VCC voltage to ensure proper operation. Once the VCC
voltage is above the UVLO threshold, the part begins
operation after an initialization routine of 50 µs. There is
no UVLO circuitry on either the PVCC or VIN rails.
(12)
Using the minimum value of C5 generally offers the best
transient response, and 100 pF is a good initial value in
many applications. However, under some operating
conditions excessive pulse jitter may be observed. To
reduce jitter and improve stability, the value of C5 can
be increased:
Over-Current Protection (OCP)
The FAN23SV04T uses current information through the
LS to implement valley-current limiting. While an OC
event is detected, the HS is prevented from turning on
and the LS is kept on until the current falls below the
user-defined set point. Once the current is below the set
point, the HS is allowed to turn on.
(13)
5 V PVCC
The ILIM pin has an open detection circuit to provide
protection against operation without a current limit.
The PVCC is the output of the internal regulator that
supplies power to the drivers and VCC. It is crucial to keep
this pin decoupled to PGND with a ≥1 µF X5R or X7R
ceramic capacitor. Because VCC powers the internal
analog circuit, it is filtered from PVCC with a 10 Ω resistor
and 0.1 µF X7R decoupling ceramic capacitor to AGND.
Over-Temperature Protection (OTP)
FAN23SV04T
incorporates
an
over-temperature
protection circuit that disables the converter when the
die temperature reaches 155°C. The IC restarts when
the die temperature falls below 140°C.
© 2011 Fairchild Semiconductor Corporation
FAN23SV04T • Rev. 1.13
www.fairchildsemi.com
12
FAN23SV04T — 4 A Synchronous Buck Regulator for DDR Termination
During normal operation, the SS voltage is clamped to
400 mV above the FB voltage. The clamp voltage drops
to 40 mV during an overload condition (when VFB is ≤
400 mV) to allow the converter to recover using the softstart ramp once the overload condition is removed. There
is no on-time modulation during normal soft-start or when
recovering from an overload condition.
(18)
The output voltage, VOUT, is regulated by initiating a highside MOSFET on-time interval when the valley of the
divided output voltage appearing at the FB pin reaches
VREF. Since this method regulates at the valley of the
output ripple voltage, the actual DC output voltage on
VOUT is offset from the programmed output voltage by the
average value of the output ripple voltage. The output
VOUT setting of the regulator can be determined using the
following equation:
where ILOAD-MAX is the maximum load current and D is
the duty cycle VOUT/VIN. The maximum ICIN(RMS) occurs
at 50% duty cycle.
The capacitance is given by:
(19)
where VIN is input voltage ripple, normally 1% of VIN.
(14)
For example: for VIN=12 V, VIN=120 mV, VOUT=0.6 V,
4 A load, and fSW=950 kHz; then CIN is calculated as
1.7 µF, select a single 10 µF, 25 V-rated ceramic
capacitor with X7R or similar dielectric, recognizing that
the capacitor DC bias characteristic indicates that the
capacitance value falls approximately 40% at V IN=12 V.
where VDDQ is the voltage applied to pin 31.
For example; if VDDQ=1.2 V thenVOUT=600mV. VFB is
trimmed
to
a
value
of
596 mV
when
VDDQ=VREF=600 mV. The final output voltage, including
the effect of the output ripple voltage, can be
approximated by:
Output Capacitor Selection
Output capacitor COUT is also selected based on voltage
rating, RMS current ICIN (RMS) rating, and capacitance.
For capacitors with DC voltage bias derating, such as
ceramic capacitors, higher rating is recommended.
(15)
When calculating COUT, usually the dominant
requirement is the current load step transient. If the
unloading transient requirement (IOUT transitioning from
HIGH to LOW), is satisfied, the load transient (IOUT
transitioning LOW to HIGH), is also usually satisfied.
The unloading COUT calculation, assuming COUT has
negligible parasitic resistance and inductance in the
circuit path, is given by:
Setting the Switching Frequency (fSW)
fSW is programmed through external RFREQ as follows:
(16)
where CtON=2.2 pF). For example; for fSW=500 kHz
and VOUT=0.6 V, then select a standard resistor value
for RFREQ=27.4 k.
(20)
Inductor Selection
where Ilevel1 and Ilevel2 are current levels before and
after load steps, and VOUT is the voltage overshoot,
usually specified at 3 to 5%.
The inductor is typically selected based on the ripple
current (IL), which is approximately 25% to 45% of the
maximum DC load. The inductor current rating should
be selected such that the saturation and heating current
ratings exceed the intended currents encountered in the
application over the expected temperature range of
operation. Regulators that require fast transient
response use smaller inductance and higher current
ripple; while regulators that require higher efficiency
keep ripple current on the low side.
For example: for VI=12 V, VOUT=0.6 V, ILEVEL1=3 A,
ILEVEL2=2 A, fSW=500 kHz, LOUT=1 µH, and 4.0% VOUT
overshoot of 24 mV; the COUT value is calculated to be
170 µF, and four 47 µF, 6.3 V-rated X5R ceramic
capacitors may be used. This equation assumes that
the load current rises instantaneously: with reduced
current slew rate, the value for COUT can be reduced.
The inductor value is given by:
Setting the Current Limit
Current limit is implemented by sensing the inductor
valley current across the LS MOSFET VDS during the LS
on-time. The current-limit comparator prevents a new
on-time from starting until the valley current is less than
the current limit.
(17)
For example: for 12 V VIN, 0.6 V VOUT, 4 A load, 25% IL,
and 500 kHz fSW; L is calculated to be 1.1 µH and a
standard value of 1 µH is selected.
The set point is configured by connecting a resistor from
the ILIM pin to the SW pin. A trimmed current is output
onto the ILIM pin, which creates a voltage across the
resistor. When the voltage on ILIM goes negative, an
over-current condition is detected.
Input Capacitor Selection
Input capacitor CIN is selected based on voltage rating,
RMS current ICIN(RMS) rating, and capacitance. For
capacitors with DC voltage bias derating, such as
ceramic capacitors, higher rating is strongly
recommended. RMS current rating is given by:
© 2011 Fairchild Semiconductor Corporation
FAN23SV04T • Rev. 1.13
www.fairchildsemi.com
13
FAN23SV04T — 4 A Synchronous Buck Regulator for DDR Termination
Setting the Output Voltage (VOUT)
should be on a common side of the PCB in close
proximity to each other and connected using surface
copper.
(21)
where KILIM is the current source scale factor, and
IVALLEY is the inductor valley current when the current
limit threshold is reached. The factor 1.02 accounts
for the temperature offset of the LS MOSFET
compared to the control circuit.
Sensitive analog components; including SS, FB, ILIM,
FREQ, and EN; should be placed away from the highvoltage switching circuits, such as SW and BOOT, and
connected to their respective pins with short traces.
The inner PCB layer closest to the FAN23SV04T device
should have Power Ground (PGND) under the powerprocessing portion of the device (PVIN, SW, and
PGND). This inner PCB layer should have a separate
Analog Ground (AGND) under the P1 pad and the
associated analog components. AGND and PGND
should be connected together near the IC between
PGND pins 18-21 and AGND pin 23, which connects to
P1 thermal pad.
With the constant on-time architecture, HS is always
turned on for a fixed on-time. This determines the peakto-peak inductor current.
Current ripple I is given by:
(22)
From the equation above, the worst-case ripple occurs
during an output short circuit (where VOUT is 0 V). This
should be taken into account when selecting the current
limit set point.
The AGND thermal pad (P1) should be connected to
AGND plane on the inner layer using four 0.25 mm vias
spread under the pad. No vias are included under PVIN
(P2) and SW (P3) to maintain the PGND plane under
the power circuitry intact.
The FAN23SV04T uses valley-current sensing. The
current limit (IILIM) set point is the valley (IVALLEY).
Power circuit loops that carry high currents should be
arranged to minimize the loop area. Primary focus
should be directed to minimize the loop for current flow
from the input capacitor to PVIN, through the internal
MOSFETs, and returning to the input capacitor. The
input capacitor should be placed as close to the PVIN
terminals as possible.
The valley current level for calculating RILIM is given by:
(23)
where ILOAD (CL) is the DC load current when the
current limit threshold is reached.
The current return path from PGND at the low-side
MOSFET source to the negative terminal of the input
capacitor can be routed under the inductor and also
through vias that connect the input capacitor and lowside MOSFET source to the PGND region under the
power portion of the IC.
For example: in a converter designed for 4 A steadystate operation and 1 A current ripple, the current-limit
threshold could be selected at 120% of ILOAD,(SS) to
accommodate transient operation and inductor value
decrease under loading. As a result; ILOAD,(SS) is 4.8 A,
IVALLEY=4.3 A, and RILIM is selected as the standard
value of1.02 k
The SW node trace that connects the source of the
high-side MOSFET and the drain of the low-side
MOSFET to the inductor should be short and wide.
Boot Resistor
To control the voltage across the output capacitor, the
output voltage divider should be located close to the FB
pin, with the upper FB voltage divider resistor connected
to the positive side of the output capacitor, and the
bottom resistor should be connected to the AGND
portion of the FAN23SV04T device.
In some applications, especially with higher input voltage,
the VSW ring voltage may exceed the derating guidelines
of 80% to 90% of absolute rating for VSW. In this situation,
a resistor can be connected in series with the boot
capacitor (C3 in Figure 1) to reduce the turn-on speed of
the high-side MOSFET to reduce the amplitude of the
VSW ring voltage.
When using ceramic capacitor solutions with external
ramp injection circuitry (R2, C4, C5 in Figure 1), R2 and
C4 should be connected near the inductor and coupling
capacitor C5 should be placed near the FB pin to
minimize FB pin trace length.
PCB (Printed Circuit Board) Layout
Guidelines
The following should be considered before beginning a
PCB layout using the FAN23SV04T. A sample PCB
layout from the evaluation board following the layout
guidelines is shown in Figure 22 - Figure 25.
Decoupling capacitors for PVCC and VCC should be
located close to their respective device pins.
SW node connections to BOOT, ILIM, and ripple
injection resistor R2 should be through separate traces.
Power components consisting of the input capacitors,
output capacitors, inductor, and FAN23SV04T device
© 2011 Fairchild Semiconductor Corporation
FAN23SV04T • Rev. 1.13
www.fairchildsemi.com
14
FAN23SV04T — 4 A Synchronous Buck Regulator for DDR Termination
RILIM is calculated by:
FAN23SV04T — 4 A Synchronous Buck Regulator for DDR Termination
Figure 22. Evaluation Board Top Layer Copper
Figure 23. Evaluation Board Inner Layer 1 Copper
© 2011 Fairchild Semiconductor Corporation
FAN23SV04T • Rev. 1.13
www.fairchildsemi.com
15
FAN23SV04T — 4 A Synchronous Buck Regulator for DDR Termination
Figure 24. Evaluation Board Inner Layer 2 Copper
Figure 25. Evaluation Board Bottom Layer Copper
© 2011 Fairchild Semiconductor Corporation
FAN23SV04T • Rev. 1.13
www.fairchildsemi.com
16
5.50±0.10
26
18
1.05±0.10
17
27
0.25±0.05 (30X)
5.00±0.10
34
0.25±0.05
0.025±0.025
10
1
9
SEATING
PLANE
PIN#1
INDICATOR
SEE
DETAIL 'A'
1.58±0.01
(0.35)
SCALE: 2:1
2.18±0.01
(0.43)
0.50±0.01
9
1
(0.25)
0.40±0.01 (30X)
(0.35) 34
10
0.68±0.01
(0.35)
3.50±0.01
2.58±0.01
(1.75)
17
(0.75)
(0.33)
(0.35)
27
0.43±0.01
18
26
(0.35)
NOTES: UNLESS OTHERWISE SPECIFIED
A) NO INDUSTRY REGISTRATION APPLIES.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) DRAWING FILE NAME: MKT-PQFN34AREV2
F) FAIRCHILD SEMICONDUCTOR
(0.25)
(0.28) (3X)
(0.24)
1.75±0.01
5.70
2.18
1.58
0.55 (30X)
2.10
(0.35)
1.80
26
18
0.55
17
27
(1.75)
2.58
4.10
3.50
3.60
(1.85)
0.68
34
10
0.75
1
(0.30)
9
(0.35)
0.50±0.05
0.43
(0.08)
4.10
LAND PATTERN
RECOMMENDATION
0.20
0.30 (30X)
5.20
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