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FAN23SV56AMPX
6 A Synchronous Buck Regulator
Description
Features
VIN Range: 7 V to 24 V Using Internal Linear
Regulator for Bias
VIN Range: 4.5 V to 5.5 V with VIN/PVIN/PVCC
Connected to Bypass Internal Regulator
High Efficiency: Over 96% Peak
Continuous Output Current: 6 A
Accurate Enable Facilitates VIN UVLO Functionality
PFM Mode for Light-Load Efficiency
Excellent Line and Load Transient Response
Precision Reference: ±1% Over Temperature
Output Voltage Range: 0.6 to 5.5 V
Programmable Frequency: 200 kHz to 1.5 MHz
Programmable Soft-Start
Low Shutdown Current
Adjustable Sourcing Current Limit
The FAN23SV56A is a highly efficient synchronous
buck regulator. The regulator is capable of operating
with an input range from 7 V to 24 V and supporting 6 A
continuous load currents. The device can operate from
a 5 V rail (±10%) if VIN, PVIN, and PVCC are connected
together to bypass the internal linear regulator.
The FAN23SV56A utilizes Fairchild’s constant on-time
control architecture to provide excellent transient
response and maintain a relatively constant switching
frequency. Pulse Frequency Modulation (PFM) Mode
maximizes light-load efficiency by reducing switching
frequency when the inductor is operating in
Discontinuous Conduction Mode (DCM) at light loads,
while clamping the minimum frequency above the
audible range with Ultrasonic Mode.
Switching frequency and over-current protection can
be programmed to provide a flexible solution for
various applications. Output over-voltage, undervoltage, over-current, and thermal shutdown protections
help prevent damage to the device during fault
conditions. A hysteresis feature restarts the device
when normal operating temperature is reached.
Internal Boot Diode
Thermal Shutdown
Halogen and Lead Free, RoHS Compliant
Applications
Mainstream Notebooks
Servers and Desktop Computers
Game Consoles
Telecommunications
Storage
Base Stations
Ordering Information
Part Number
Configuration
FAN23SV56AMPX PFM with Ultrasonic Mode
© 2015 Fairchild Semiconductor Corporation
FAN23SV56A • Rev. 1.0
Operating
Temperature Range
Output
Current (A)
-40 to 125°C
6
Package
34-Lead, PQFN, 5.5 mm
x 5.0 mm
www.fairchildsemi.com
FAN23SV56AMPX — 6 A Synchronous Buck Regulator
September 2015
VIN = 19V
VIN = 19V
R11
10Ω
C9
0.1µF
C10
2.2µF
CIN
0.1µF
R7
61.9kΩ
PVCC
VCC
Ext
EN
VIN
PVIN
C3
0.1µF
EN
R7, R8 used for Accurate EN
R7, R8 open for Ext EN
CIN
2x10µF
R8
10kΩ
L1
1.2µH
SW
PGOOD
ILIM
SOFT START
R2
1.5kΩ
R5 1.65kΩ
C7
15nF
VOUT = 1.2V
IOUT=0-6A
BOOT
FAN23SV56A
C4
0.1µF
C5
100pF
FREQ
R3
10kΩ
COUT
4x47µF
FB
R9
54.9kΩ
AGND
R6
4.99kΩ
PGND
R4
10kΩ
Figure 1. Typical Application with VIN = 19 V
VIN = 5V
R11
10Ω
C9
0.1µF
PVCC
VCC
Ext
EN
C10
2.2µF
CIN
0.1µF
VIN
CIN
2x10µF
PVIN
C3
0.1µF
EN
FAN23SV56A
VOUT = 1.2V
IOUT=0-6A
BOOT
L1
1.2µH
SW
PGOOD
ILIM
SOFT START
R5 1.65kΩ
C7
15nF
FAN23SV56AMPX — 6 A Synchronous Buck Regulator
Typical Application Diagrams
R2
1.5kΩ
C4
0.1µF
C5
100pF
FREQ
R3
10kΩ
COUT
4x47µF
FB
R9
54.9kΩ
AGND
R6
4.99kΩ
PGND
R4
10kΩ
Figure 2. Typical Application with VIN=5 V
© 2015 Fairchild Semiconductor Corporation
FAN23SV56A • Rev. 1.0
www.fairchildsemi.com
2
FAN23SV56AMPX — 6 A Synchronous Buck Regulator
Functional Block Diagram
VIN
BOOT
PVIN
PVCC
Linear
Regulator
PVCC
VCC
VCC
VCC UVLO
1.26V/1.14V
PVCC
EN
ENABLE
VCC
VCC
10µA
Modulator
HS Gate
Driver
SS
FB
FB
Comparator
VREF
SW
FREQ
PFM
Comparator
Control
Logic
x1.2
2nd Level OVP
Comparator
PVCC
st
x1.1
1 Level OVP
Comparator
x0.9
Under-Voltage
Comparator
LS Gate
Driver
VCC
PGOOD
Thermal
Shutdown
10µA
Current Limit
Comparator
AGND
ILIM
PGND
Figure 3. Block Diagram
© 2015 Fairchild Semiconductor Corporation
FAN23SV56A • Rev. 1.0
www.fairchildsemi.com
3
AGND
(P1)
SW
(P3)
PGOOD 30
SW
12
32
FREQ
13
SW
SW 13
31
SS
14
SW
SW
30 PGOOD
29
EN
28
NC
27
FB
14
18
PGND
PGND
PGND
PGND
SW 17
SW
SW
AGND
17
ILIM
27
PVCC
FB
VCC
VIN
SW
SW 16
19
SW
12
SW
20
BOOT
NC
16
21
AGND
33
28
22
PVIN
PVIN 11
NC
23
PVIN
PVIN
SW
24
1
11
15
25
2
NC
29
26
3
34
SW 15
EN
4
Figure 4. Pin Assignments(Bottom View)
18
19
20
21
22
23
24
25
26
VCC
31
5
PVCC
SS
6
ILIM
32
7
PVIN 10
AGND
FREQ
8
PVIN
SW
33
9
10
PGND
NC
PVIN
(P2)
PVIN
9
PGND
8
PVIN
7
PGND
6
PVIN
PVIN
5
PVIN
AGND
4
PVIN
BOOT
3
PVIN
SW
2
PVIN
VIN
1
34
PGND
NC
Figure 5. Pin Assignments(Top View)
Pin Definitions
Name
Pad / Pin
PVIN
P2, 5-11
VIN
1
Power input to the linear regulator; used in the modulator for input voltage feed-forward
PVCC
25
Power output of the linear regulator; directly supplies power for the low-side gate driver
and boot diode. Can be connected to VIN and PVIN for operation from 5 V rail.
Power supply input for the controller
VCC
26
PGND
18-21
AGND
P1, 4, 23
SW
Description
Power input for the power stage
Power ground for the low-side power MOSFET and for the low-side gate driver
Analog ground for the analog portions of the IC and for substrate
P3, 2, 12-17, 22 Switching node; junction between high-and low-side MOSFETs
BOOT
3
Supply for high-side MOSFET gate driver. A capacitor from BOOT to SW supplies the
charge to turn on the N-channel high-side MOSFET. During the freewheeling interval
(low-side MOSFET on), the high-side capacitor is recharged by an internal diode
connected to PVCC.
ILIM
24
Current limit. A resistor between ILIM and SW sets the current limit threshold.
FB
27
Output voltage feedback to the modulator
EN
29
Enable input to the IC. Pin must be driven logic HIGH to enable or logic LOW to
disable.
SS
31
Soft-start input to the modulator
FREQ
32
On-time and frequency programming pin. Connect a resistor between FREQ and
AGND to program on-time and switching frequency.
PGOOD
30
Power good; open-drain output indicating VOUT is within set limits.
NC
28, 33-34
Leave pin open or connect to AGND.
© 2015 Fairchild Semiconductor Corporation
FAN23SV56A • Rev. 1.0
www.fairchildsemi.com
4
FAN23SV56AMPX — 6 A Synchronous Buck Regulator
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VPVIN
VIN
VBOOT
VSW
VBOOT
Parameter
Conditions
Min.
Max.
Unit
Power Input
Referenced to PGND
-0.3
30.0
V
Modulator Input
Referenced to AGND
-0.3
30.0
V
Referenced to PVCC
-0.3
30.0
V
Referenced to PVCC, +11% of VREF (666 mV), both HS and LS
turn off. By turning off the LS during an OV event, V OUT
overshoot can be reduced when there is positive
inductor current by increasing the rate of discharge.
Once the VFB voltage falls below VREF, the latched OV
signal is cleared and operation returns to normal.
(12)
The minimum value of C5 can be selected to minimize
the capacitive component of ripple appearing on the
feedback pin:
A second over-voltage detection is implemented to
protect the load from more serious failure. When VFB
rises +22% above the VREF (732 mV), the HS latches off
until a power cycle on VCC and the LS is forced on until
530 mV of VFB.
(13)
Using the minimum value of C5 generally offers the best
transient response, and 100 pF is a good initial value in
many applications. Under some operating conditions,
excessive pulse jitter may be observed. To reduce jitter
and improve stability, the value of C5 can be increased:
Over-Temperature Protection (OTP)
The FAN23SV56A incorporates an over-temperature
protection circuit that disables the converter when the
die temperature reaches 155°C. The IC restarts when
the die temperature falls below 140°C.
(14)
5 V PVCC
Power Good (PGOOD)
The PVCC is the output of the internal regulator that
supplies power to the drivers and VCC. It is crucial to keep
this pin decoupled to PGND with a ≥1 µF X5R or X7R
ceramic capacitor. Because VCC powers internal analog
circuit, it is filtered from PVCC with a 10 Ω resistor and
0.1 µF X7R decoupling ceramic capacitor to AGND.
The PGOOD pin serves as an indication to the system
that the output voltage of the regulator is stable and
within regulation. Whenever VOUT is outside the
regulation window or the regulator is at overtemperature (UV, OV, and OT), the PGOOD pin is
pulled LOW.
Setting the Output Voltage (VOUT)
PGOOD is an open-drain output that asserts LOW when
VOUT is out of regulation or when OT is detected.
The output voltage VOUT is regulated by initiating a highside MOSFET on-time interval when the valley of the
divided output voltage appearing at the FB pin reaches
VREF. Since this method regulates at the valley of the
output ripple voltage, the actual DC output voltage on
VOUT is offset from the programmed output voltage by
the average value of the output ripple voltage. The initial
regulator VOUT setting can be programmed from 0.6 V to
5.5 V by an external resistor divider (R3 and R4):
Application Information
Stability
Constant on-time stability consists of two parameters:
stability criterion and sufficient signal at VFB.
Stability criterion is given by:
(9)
(15)
Sufficient signal requirement is given by:
where VREF is 600 mV.
(10)
For example; for 1.2 V VOUT and 10 k R3, then R4 is
10 k. For 600 mV VOUT, R4 is left open. VFB is trimmed
to a value of 596 mV when VREF=600 mV, so the final
output voltage, including the effect of the output ripple
voltage, can be approximated by the equation:
where IIND is the inductor current ripple and VFB is
the ripple voltage on VFB, which should be ≥12 mV.
In certain applications, especially designs utilizing only
ceramic output capacitors, there may not be sufficient
ripple magnitude available on the feedback pin for
stable operation. In this case, an external circuit
consisting of 2 resistors (R2 and R6) and 2 capacitors
(C4 and C5) can be added to inject ripple voltage into
the FB pin (See Figure 1).
(16)
There are some specific considerations when selecting
the RCC ripple injector circuit. For typical applications,
use 4.99 kΩ for R6, the value of C4 can be selected as
0.1 µF and approximate values for R2 and C5 can be
determined using the following equations.
© 2015 Fairchild Semiconductor Corporation
FAN23SV56A • Rev. 1.0
www.fairchildsemi.com
15
FAN23SV56AMPX — 6 A Synchronous Buck Regulator
Under-Voltage Protection (UVP)
If VFB is below the under-voltage threshold of -11% VREF
(534 mV), the part enters UVP and PGOOD pulls LOW.
fSW is programmed through external RFREQ as follows:
When calculating COUT, usually the dominant
requirement is the current load step transient. If the
unloading transient requirement (IOUT transitioning from
HIGH to LOW), is satisfied, then the load transient (IOUT
transitioning LOW to HIGH), is also usually satisfied.
The unloading COUT calculation, assuming COUT has
negligible parasitic resistance and inductance in the
circuit path, is given by:
(17)
where CtON=2.2 pF internal capacitor that generates
tON. For example; for fSW=500 kHz and VOUT=1.2 V,
select a standard value for RFREQ=54.9 k.
Inductor Selection
The inductor is typically selected based on the ripple
current (IL), which is usually selected as 25% to 45% of
the maximum DC load. The inductor current rating
should be selected such that the saturation and heating
current ratings exceed the intended currents
encountered in the application over the expected
temperature range of operation. Regulators that require
fast transient response use smaller inductance and
higher current ripple; while regulators that require higher
efficiency keep ripple current on the low side.
(21)
where IMAX and IMIN are maximum and minimum load
steps, respectively and VOUT is the voltage
overshoot, usually specified at 3 to 5%.
For example: for 19 V VIN, 1.2V VOUT, 6 A load, 30% IL,
and 500 kHz fSW; L is 1.2 µH.
For example: for VI=19 V, VOUT=1.2 V, 4 A IMAX, 2 A IMIN,
fSW=500 kHz, LOUT=1.2 µH, and 3% VOUT ripple of
36 mV; the COUT value is calculated to be 164 µF. This
capacitor requirement can be satisfied using four 47 µF,
6.3 V-rated, X5R ceramic capacitors. This calculation
applies for load current slew rates faster than the
inductor current slew rate, which can be defined as
VOUT/L during the load current removal. For reducedload-current slew rates and/or reduced transient
requirements, the output capacitor value may be
reduced and comprised of low-cost 22 µF capacitors.
Input Capacitor Selection
Setting the Current Limit
Input capacitor CIN is selected based on voltage rating,
RMS current ICIN(RMS) rating, and capacitance. For
capacitors having DC voltage bias derating, such as
ceramic capacitors, higher rating is strongly
recommended. RMS current rating is given by:
Current limit is implemented by sensing the inductor
valley current across the LS MOSFET VDS during the LS
on-time. The current limit comparator prevents a new
on-time from being started until the valley current is less
than the current limit.
The inductor value is given by:
(18)
The set point is configured by connecting a resistor from
the ILIM pin to the SW pin. A trimmed current is output
onto the ILIM pin, which creates a voltage across the
resistor. When the voltage on ILIM goes negative, an
over-current condition is detected.
(19)
where ILOAD-MAX is the maximum load current and D is
the duty cycle VOUT/VIN. The maximum ICIN(RMS) occurs
at 50% duty cycle.
RILIM is calculated by:
The capacitance is given by:
(22)
(20)
where KILIM is the current source scale factor, and
IVALLEY is the inductor valley current when the current
limit threshold is reached. The factor 1.02 accounts
for the temperature offset of the LS MOSFET
compared to the control circuit.
where VIN is the input voltage ripple, normally 1%
of VIN.
For example; for VIN=19 V, VIN=190 mV, VOUT=1.2 V,
6 A load, and fSW=500 kHz; CIN is 4 µF and is ICIN(RMS) is
1.45 ARMS. Select one 10 µF25 V-rated ceramic
capacitor with X7R or similar dielectric, recognizing that
the capacitor DC bias characteristic indicates that the
capacitance value falls approximately 60% at VIN=19 V.
Also, the 10 µF X7R capacitor can carry over 3 ARMS in
the frequency range from 100 kHz to 1 MHz, exceeding
the input capacitor current rating requirements. An
additional 1 µF capacitor may be needed to suppress
noise generated by high frequency switching transitions.
With the constant on-time architecture, HS is always
turned on for a fixed on-time; this determines the peakto-peak inductor current.
Current ripple I is given by:
(23)
From the equation above, the worst-case ripple occurs
during an output short circuit (where VOUT is 0 V). This
should be taken into account when selecting the current
limit set point.
Output Capacitor Selection
Output capacitor COUT is also selected based on voltage
rating, RMS current ICOUT(RMS) rating, and capacitance.
© 2015 Fairchild Semiconductor Corporation
FAN23SV56A • Rev. 1.0
www.fairchildsemi.com
16
FAN23SV56AMPX — 6 A Synchronous Buck Regulator
For capacitors having DC voltage bias derating, such as
ceramic capacitors, higher rating is highly recommended.
Setting the Switching Frequency (fSW)
The inner PCB layer closest to the FAN23SV56A device
should have power ground (PGND) under the power
processing portion of the device (PVIN, SW, and
PGND). This inner PCB layer should have a separate
analog ground (AGND) under the P1 pad and the
associated analog components. AGND and PGND
should be connected together near the IC between
PGND pins 18-21 and AGND pin 23, which connects to
P1 thermal pad.
The valley current level for calculating RILIM is given by:
(24)
where ILOAD (CL) is the DC load current when the
current limit threshold is reached.
The AGND thermal pad (P1) should be connected to
AGND plane on the inner layer using four 0.2 5mm vias
spread under the pad. No vias are included under PVIN
(P2) and SW (P3) to maintain the PGND plane under
the power circuitry intact.
For example: In a converter designed for 6 A steadystate operation and 1.8 A current ripple, the current-limit
threshold could be selected at 120% of ILOAD,(MAX) to
accommodate transient operation and inductor value
decrease under loading. As a result, ILOAD,(MAX) is 7.2 A,
IVALLEY=6.3 A, and RILIM is selected as the standard
value of 1.65 k
Power circuit loops that carry high currents should be
arranged to minimize the loop area. Primary focus
should be directed to minimize the loop for current flow
from the input capacitor to PVIN, through the internal
MOSFETs, and returning to the input capacitor. The
input capacitor should be placed as close to the PVIN
terminals as possible.
Boot Resistor
In some applications, especially with higher input
voltage, the VSW ring voltage may exceed derating
guidelines of 80% to 90% of absolute rating for V SW. In
this situation, a resistor can be connected in series with
boot capacitor (C3 in Figure 1) to reduce the turn-on
speed of the high-side MOSFET to reduce the
amplitude of the VSW ring voltage.
The current return path from PGND at the low-side
MOSFET source to the negative terminal of the input
capacitor can be routed under the inductor and also
through vias that connect the input capacitor and lowside MOSFET source to the PGND region under the
power portion of the IC.
If necessary, a resistor and capacitor snubber can be
added from VSW to PGND to reduce the magnitude of
the ringing voltage. Please contact Fairchild Customer
Support for assistance selecting a boot resistor or
snubber circuit in applications that operate above a 21 V
typical input voltage.
The SW node trace that connects the source of the
high-side MOSFET and the drain of the low-side
MOSFET to the inductor should be short and wide.
To control the voltage across the output capacitor, the
output voltage divider should be located close to the FB
pin, with the upper FB voltage divider resistor connected
to the positive side of the output capacitor and the
bottom resistor connected to the AGND portion of the
FAN23SV56A device.
PCB (Printed Circuit Board) Layout
Guidelines
The following points should be considered before
beginning a PCB layout. A sample PCB layout from the
evaluation board is shown in Figure 26 through Figure 29
following these layout guidelines.
When using ceramic capacitor solutions with external
ramp injection circuitry (R2, C4, C5 in Figure 1); R2 and
C4 should be connected near the inductor. Coupling
capacitor C5 should be placed near FB pin to minimize
FB pin trace length.
Power components consisting of the input capacitors,
output capacitors, inductor, and FAN23SV56A device
should be placed on a common side of the PCB near
each other and connected using surface copper.
Decoupling capacitors for PVCC and VCC should be
located close to their respective device pins.
Sensitive analog components such as SS, FB, ILIM,
FREQ, and EN should be placed away from the highvoltage switching circuits, such as SW and BOOT, and
connected to their respective pins with short traces.
© 2015 Fairchild Semiconductor Corporation
FAN23SV56A • Rev. 1.0
SW node connections to BOOT, ILIM, and ripple
injection resistor R2 should be through separate traces.
www.fairchildsemi.com
17
FAN23SV56AMPX — 6 A Synchronous Buck Regulator
The FAN23SV56A uses valley-current sensing, the
current limit (IILIM) set point is the valley (IVALLEY).
FAN23SV56AMPX — 6 A Synchronous Buck Regulator
Figure 26. Evaluation Board Top Layer Copper
Figure 27. Evaluation Board Inner Layer 1 Copper
© 2015 Fairchild Semiconductor Corporation
FAN23SV56A • Rev. 1.0
www.fairchildsemi.com
18
FAN23SV56AMPX — 6 A Synchronous Buck Regulator
Figure 28. Evaluation Board Inner Layer 2 Copper
Figure 29. Evaluation Board Bottom Layer Copper
© 2015 Fairchild Semiconductor Corporation
FAN23SV56A • Rev. 1.0
www.fairchildsemi.com
19
5.50±0.10
26
18
1.05±0.10
17
27
0.25±0.05 (30X)
5.00±0.10
34
0.25±0.05
0.025±0.025
10
1
9
SEATING
PLANE
PIN#1
INDICATOR
SEE
DETAIL 'A'
1.58±0.01
(0.35)
SCALE: 2:1
2.18±0.01
(0.43)
0.50±0.01
9
1
(0.25)
0.40±0.01 (30X)
(0.35) 34
10
0.68±0.01
(0.35)
3.50±0.01
2.58±0.01
(1.75)
17
(0.75)
(0.33)
(0.35)
27
0.43±0.01
18
26
(0.35)
NOTES: UNLESS OTHERWISE SPECIFIED
A) NO INDUSTRY REGISTRATION APPLIES.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) DRAWING FILE NAME: MKT-PQFN34AREV2
F) FAIRCHILD SEMICONDUCTOR
(0.25)
(0.28) (3X)
(0.24)
1.75±0.01
5.70
2.18
1.58
0.55 (30X)
2.10
(0.35)
1.80
26
18
0.55
17
27
(1.75)
2.58
4.10
3.50
3.60
(1.85)
0.68
34
10
0.75
1
(0.30)
9
(0.35)
0.50±0.05
0.43
(0.08)
4.10
LAND PATTERN
RECOMMENDATION
0.20
0.30 (30X)
5.20
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
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