FAN23SV65AMPX
Buck Regulator,
Synchronous, 15 A
Description
The FAN23SV65A is a highly efficient synchronous buck regulator.
The regulator is capable of operating with an input range from 7 V to
24 V and supporting up to 15 A continuous load currents. The device
can operate from a 5 V rail (±10%) if VIN, PVIN, and PVCC are
connected together to bypass the internal linear regulator.
The FAN23SV65A utilizes ON Semiconductor’s constant on−time
control architecture to provide excellent transient response and to
maintain a relatively constant switching frequency. This device
utilizes Pulse Frequency Modulation (PFM) mode to maximize
light−load efficiency by reducing switching frequency when the
inductor is operating in discontinuous conduction mode at light loads,
while clamping the minimum frequency above the audible range with
ultrasonic mode.
Switching frequency and over−current protection can be
programmed to provide a flexible solution for various applications.
Output over−voltage, under−voltage, over−current, and thermal
shutdown protections help prevent damage to the device during fault
conditions. After thermal shutdown is activated, a hysteresis feature
restarts the device when normal operating temperature is reached.
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PQFN34
CASE 483AM
MARKING DIAGRAM
$Y&Z&3&K
FAN23
SV65A
Features
• VIN Range: 7 V to 24 V Using Internal Linear Regulator for Bias
• VIN Range: 4.5 V to 5.5 V with VIN/PVIN/PVCC Connected to Bypass
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Internal Regulator
High Efficiency: Over to 96% Peak
Continuous Output Current: 15 A
Internal Linear Bias Regulator
Accurate Enable Facilitates VIN UVLO Functionality
PFM Mode for Light−Load Efficiency
Excellent Line and Load Transient Response
Precision Reference: ±1% Over Temperature
Output Voltage Range: 0.6 to 5.5 V
Programmable Frequency: 200 kHz to 1 MHz
Programmable Soft−Start
Low Shutdown Current
Adjustable Sourcing Current Limit
Internal Boot Diode
Thermal Shutdown
Halogen and Lead Free, RoHS Compliant
$Y
&Z
&3
&K
FAN23SV65A
= Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
= Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Applications
•
•
•
•
•
•
Mainstream Notebooks
Servers and Desktop Computers
Game Consoles
Telecommunications
Storage
Base Stations
© Semiconductor Components Industries, LLC, 2015
June, 2018 − Rev. 2
1
Publication Order Number:
FAN23SV65AMPX/D
FAN23SV65AMPX
ORDERING INFORMATION
Part Number
Configuration
Operating
Temperature Range
Output Current (A)
Package
FAN23SV65AMPX
PFM with Ultrasonic Mode
−40 to 125°C
15
34−Lead,
PQFN, 5.5 mm x 5.0 mm
TYPICAL APPLICATION DIAGRAMS
VIN = 19V
VIN = 19 V
R11
10
C9
0.1 F
R7
64.9 k
PVCC
VCC
Ext
EN
C10
2.2 F
CIN
0.1 F
VIN
PVIN
C3
0.1 F
EN
R7, R8 used for Accurate EN
R7, R8 open for Ext EN
CIN
4x10 F
R8
10 k
BOOT
FAN23SV65A
SW
PGOOD
ILIM
SOFT−START
R2
1.5 k
R5 1.47 k
C7
15 nF
FB
AGND
C4
0.1 F
C5
100 pF
FREQ
R9
54.9 k
VOUT = 1.2 V
IOUT = 0 − 15 A
L1
0.56 H
R6
4.99 k
PGND
R3
10 k
COUT
8x47 F
R4
10 k
Figure 1. Typical Application with VIN = 19 V
VIN = 5 V
R11
10
C9
0.1 F
PVCC
VCC
Ext
EN
C10
2.2 F
CIN
0.1 F
VIN
PVIN
C3
0.1 F
EN
BOOT
FAN23SV65A
ILIM
SOFT−START
R5 1.47 k
R2
1.5 k
C5
100 pF
FREQ
R9
54.9 k
FB
AGND
VOUT = 1.2 V
IOUT = 0 − 15 A
L1
0.56 H
SW
PGOOD
C7
15 nF
CIN
4x10 F
R6
4.99 k
PGND
Figure 2. Typical Application with VIN = 5 V
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2
C4
0.1 F
R3
10 k
R4
10 k
COUT
8x47 F
FAN23SV65AMPX
FUNCTIONAL BLOCK DIAGRAM
VIN
BOOT
PVIN
PVCC
Linear
Regulator
PVCC
VCC
VCC
VCC UVLO
1.26V/1.14V
PVCC
EN
ENABLE
VCC
VCC
10mA
Modulator
HS Gate
Driver
SS
FB
FB
Comparator
VREF
SW
FREQ
PFM
Comparator
Control
Logic
x1.2
x1.1
x0.9
2nd Level OVP
Comparator
PVCC
Level OVP
Comparator
1st
LS Gate
Driver
Under−Voltage
Comparator
VCC
PGOOD
Thermal
Shutdown
10mA
Current Limit
Comparator
ILIM
AGND
Figure 3. Block Diagram
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3
PGND
FAN23SV65AMPX
9
VIN
PVIN
8
SW
PVIN
7
BOOT
PVIN
6
AGND
PVIN
5
PVIN
PVIN
4
PVIN
AGND
3
PVIN
BOOT
2
PVIN
SW
1
PVIN
VIN
PIN CONFIGURATION
9
8
7
6
5
4
3
2
1
33
NC
12
SW
SW
32
FREQ
13
SW
SW 13
31
SS
14
SW
SW 14
30 PGOOD
29
15
SW
SW 15
29
EN
NC
28
16
SW
SW 16
28
NC
FB
27
17
SW
SW 17
27
FB
32
SS
31
AGND
(P1)
SW
(P3)
26
25
24
23
22
21
20
19
18
PVCC
ILIM
AGND
SW
PGND
PGND
PGND
PGND
EN
VCC
PGOOD 30
18
PGND
FREQ
Figure 4. Pin Assignment (Bottom View)
19
20
21
22
23
24
25
26
VCC
PVIN 11
PVCC
PVIN
33
ILIM
11
NC
AGND
NC
SW
34
PVIN
(P2)
PGND
PVIN 10
PGND
PVIN
PGND
10
34
NC
Figure 5. Pin Assignment (Top View)
PIN DEFINITIONS
Name
Pad / Pin
PVIN
P2, 5−11
VIN
1
Power input to the linear regulator; used in the modulator for input voltage feed−forward
PVCC
25
Power output of the linear regulator; directly supplies power for the low−side gate driver
and boot diode. Can be connected to VIN and PVIN for operation from 5 V rail
VCC
26
Power supply input for the controller
PGND
18−21
AGND
P1, 4, 23
Analog ground for the analog portions of the IC and for substrate
SW
P3, 2, 12−17, 22
Switching node; junction between high−and low−side MOSFETs
BOOT
3
ILIM
24
Current limit. A resistor between ILIM and SW sets the current limit threshold
FB
27
Output voltage feedback to the modulator
EN
29
Enable input to the IC. Pin must be driven logic high to enable, or logic low to disable
Soft−start input to the modulator
SS
31
FREQ
32
PGOOD
30
NC
28, 33−34
Description
Power input for the power stage
Power ground for the low−side power MOSFET and for the low−side gate driver
Supply for high−side MOSFET gate driver. A capacitor from BOOT to SW supplies the
charge to turn on the N−channel high−side MOSFET. During the freewheeling interval
(low−side MOSFET on), the high−side capacitor is recharged by an internal diode
connected to PVCC
On−time and frequency programming pin. Connect a resistor between FREQ and AGND
to program on−time and switching frequency
Power good; open−drain output indicating VOUT is within set limits
Leave pin open or connect to AGND
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4
FAN23SV65AMPX
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, Unless otherwise specified)
Symbol
VPVIN
VIN
VBOOT
VSW
Parameter
Conditions
Min.
Max.
Unit
Power Input
Referenced to PGND
−0.3
30.0
V
Modulator Input
Referenced to AGND
−0.3
30.0
V
Boot Voltage
Referenced to PVCC
−0.3
30.0
V
Referenced to PVCC, < 20 ns
−0.3
33.0
V
Referenced to PGND, AGND
−1
30.0
V
Referenced to PGND, AGND < 20 ns
−5
30.0
V
SW Voltage to GND
Boot to SW Voltage
Referenced to SW
−0.3
6.0
V
Boot to PGND
Referenced to PGND
−0.3
30
V
VPVCC
Gate Drive Supply Input
Referenced to PGND, AGND
−0.3
6.0
V
VVCC
Controller Supply Input
Referenced to PGND, AGND
−0.3
6.0
V
VILIM
Current Limit Input
Referenced to AGND
−0.3
6.0
V
VFB
Output Voltage Feedback Referenced to AGND
−0.3
6.0
V
VEN
Enable Input
Referenced to AGND
−0.3
6.0
V
VSS
Soft Start Input
Referenced to AGND
−0.3
6.0
V
VFREQ
Frequency Input
Referenced to AGND
−0.3
6.0
V
Power Good Output
Referenced to AGND
−0.3
6.0
V
Electrostatic Discharge
Human Body Model, JESD22−A114
1000
V
Charged Device Model, JESD22−C101
2500
V
+150
°C
+150
°C
VBOOT
VPGOOD
ESD
TJ
Junction Temperature
TSTG
Storage Temperature
−55
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
VPVIN
Parameter
Conditions
Min
Max.
Unit
Power Input
Referenced to PGND
7
24
V
VIN
Modulator Input
Referenced to AGND
7
24
V
TJ
Junction Temperature
−40
+125
°C
20
A
5.5
V
ILOAD
VPVIN, VIN,
VPVCC
Load Current
PVIN, VIN, and Gate Drive Supply Input
TA = 25°C, No Airflow
VPVIN, VIN, VPVCC Connected for 5 V
Rail Operation and Referenced to
PGND, AGND
4.5
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
FAN23SV65AMPX
THERMAL CHARACTERISTICS
(The thermal characteristics were evaluated on a 4−layer pcb structure (1 oz/1 oz/1 oz/1 oz) measuring 7 cm x 7 cm).
Symbol
Parameter
Typ.
Unit
JA
Thermal Resistance, Junction−to−Ambient
35
°C/W
JC
Thermal Characterization Parameter, Junction−to−Top of Case
2.7
°C/W
Thermal Characterization Parameter, Junction−to−PCB
2.3
°C/W
JPCB
ELECTRICAL CHARACTERISTICS (Unless otherwise noted; VIN = 12 V, VOUT=1.2 V, and TA = TJ = −40 to +125°C. (Note 2)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
SUPPLY CURRENT
IVIN,SD
Shutdown Current
EN = 0 V
16
A
IVIN,Q
Quiescent Current
EN = 5 V, Not Switching
1.8
mA
Gate Charge Current
EN =5 V, fsw = 500 kHz
IVIN,GateCharge
22
mA
LINEAR REGULATOR
VREG
Regulator Output Voltage
IREG
Regulator Current Limit
4.75
5.05
5.25
60
V
mA
REFERENCE, FEEDBACK COMPARATOR
VFB
FB Voltage Trip Point
590
596
602
mV
IFB
FB Pin Bias Current
−100
0
100
nA
20
%
374
ns
MODULATOR
On−Time Accuracy
tON
RFREQ = 56.2 k,
VIN=10 V,
tON=250 ns, No Load
−20
tOFF,MIN
Minimum SW Off−Time
320
tON,MIN
Minimum SW On−Time
45
ns
0
%
DMIN
Minimum Duty Cycle
fMINF
Minimum Frequency Clamp
FB = 1 V
18.2
25.4
32.7
kHz
10
13
A
100
%
SOFT−START
ISS
tON,SSMOD
Soft−Start Current
SS = 0.5 V
7
SS On−Time Modulation
SS < 0.6 V
25
VSSCLAMP,NOM Nominal Soft−Start Voltage
Clamp
VSSCLAMP,OVL
Soft−Start Voltage Clamp in
Overload Condition
VFB = 0.6 V
VFB=0.3 V,
OC Condition
400
mV
40
mV
PFM ZERO−CROSSING DETECTION COMPARATOR
VOFF
ZCD Offset Voltage
TA = TJ = 25°C
−6
0
mV
−10
10
%
1
mV
CURRENT LIMIT
ILIM
VILIM,OFFSET
Valley Current Limit Accuracy
TA = TJ = 25°C,
IVALLEY=18 A
Comparator Offset
KILIM
ILIM Set−Point Scale Factor
ILIMTC
Temperature Coefficient
−1
85
4000
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6
ppm/°C
FAN23SV65AMPX
ELECTRICAL CHARACTERISTICS (Unless otherwise noted; VIN = 12 V, VOUT=1.2 V, and TA = TJ = −40 to +125°C. (Note 2)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
1.11
1.26
1.43
V
ENABLE
VTH+
VHYST
VTH−
Rising Threshold
Hysteresis
122
Falling Threshold
VENCLAMP
Enable Voltage Clamp
IENCLAMP
Clamp Current
IEN = 20 A
1.00
1.14
4.3
4.5
mV
1.28
V
V
24
A
IENLK
Enable Pin Leakage
EN = 1.2 V
100
nA
IENLK
Enable Pin Leakage
EN = 5 V
76
A
4.4
V
UVLO
VON
VCC Good Threshold Rising
VHYS
Hysteresis Voltage
160
mV
FAULT PROTECTION
VUVP
PGOOD UV Trip Point
On FB Falling
86
89
92
%
VVOP1
PGOOD OV Trip Point
On FB Rising
108
111
115
%
VOVP2
Second OV Trip Point
On FB Rising; LS = On
118
122
125
%
125
2.03
ms
1
A
RPGOOD
PGOOD Pull−Down Resistance IPGOOD = 2 mA
tPG,SSDELAY
PGOOD Soft−Start Delay
IPG,LEAK
PGOOD Leakage Current
0.82
1.42
THERMAL SHUTDOWN
TOFF
Thermal Shutdown Trip Point
(Note 1)
155
°C
THYS
Hysteresis (Note 1)
15
°C
INTERNAL BOOTSTRAP DIODE
VFBOOT
Forward Voltage
IF = 10 mA
0.6
V
IR
Reverse Leakage
VR = 24 V
1000
A
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design; not production tested.
2. Device is 100% production tested at TA = 25°C. Limits over that temperature are guaranteed by design.
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FAN23SV65AMPX
TYPICAL PERFORMANCE CHARACTERISTICS
Tested using evaluation board circuit shown in Figure 1 with VIN = 19 V, VOUT = 1.2 V, Fsw = 500 kHz, TA = 25°C, and no airflow;
unless otherwise specified.
90
90
80
80
Efficiency (%)
100
Efficiency (%)
100
70
60
50
19VIN_5VOUT_500KHZ_1.2UH
40
19VIN_3.3VOUT_500KHZ_1.2UH
60
50
19VIN_1.2VOUT_500KHZ_0.56UH
30
20
70
19VIN_1.05VOUT_500KHZ_0.4UH
0.01
0.1
1
12VIN_3.3VOUT_500KHZ_1.2UH
30
12VIN_1.05VOUT_500KHZ_0.4UH
0.01
Figure 6. Efficiency vs. Load Current with VIN = 19 V
and fSW = 500 kHz
90
80
80
Efficiency (%)
90
Efficiency (%)
100
70
60
19VIN_1.2VOUT_300KHZ_0.72UH
10
20
60
50
12VIN_1.2VOUT_300KHZ_0.72UH
12VIN_1.2VOUT_500KHZ_0.56UH
30
19VIN_1.2VOUT_1MHZ_0.3UH
12VIN_1.2VOUT_1MHZ_0.3UH
20
20
0.01
0.1
1
Load Current (A)
0.01
10
Figure 8. Efficiency vs. Load Current with
VIN = 19 V and VOUT = 1.2 V
100
100
90
90
80
19VIN_5VOUT_500KHZ_1.2UH
70
19VIN_3.3VOUT_500KHZ_1.2UH
19VIN_1.2VOUT_300KHZ_0.72UH
19VIN_1.2VOUT_500KHZ_0.56UH
60
5
10
15
Load Current (A)
10
12VIN_1.05VOUT_500KHZ_0.4UH
70
12VIN_1.2VOUT_300KHZ_0.72UH
12VIN_1.2VOUT_500KHZ_0.56UH
12VIN_1.2VOUT_1MHZ_0.3UH
12VIN_3.3VOUT_500KHZ_1.2UH
12VIN_5VOUT_500KHZ_1.2UH
19VIN_1.2VOUT_1MHZ_0.3UH
0
1
Load Current (A)
80
60
19VIN_1.05VOUT_500KHZ_0.4UH
50
0.1
Figure 9. Efficiency vs. Load Current with
VIN = 12 V and VOUT = 1.2 V
Efficiency (%)
Efficiency (%)
1
Load Current (A)
70
40
19VIN_1.2VOUT_500KHZ_0.56UH
30
0.1
Figure 7. Efficiency vs. Load Current with VIN = 12 V
and fSW = 500 kHz
100
40
12VIN_1.2VOUT_500KHZ_0.56UH
20
10 20
Load Current (A)
50
12VIN_5VOUT_500KHZ_1.2UH
40
50
20
0
Figure 10. Efficiency vs. Load Current with
VIN = 19 V
5
10
15
Load Current (A)
20
Figure 11. Efficiency vs. Load Current with
VIN = 12 V
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FAN23SV65AMPX
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Tested using evaluation board circuit shown in Figure 1 with VIN = 19 V, VOUT = 1.2 V, Fsw = 500 kHz, TA = 25°C, and no airflow;
unless otherwise specified.
80
19VIN_1.2VOUT_1MHz_0.3uH
80
Case Temperature Rise (°C)
Case Temperature Rise (°C)
90
19VIN_1.2VOUT_500kHz_0.56uH
70
19Vin_1.2Vout_300kHz_0.72uH
60
50
40
30
20
10
12VIN_1.2VOUT_500kHz_0.56uH
60
12VIN_1.2VOUT_300kHz_0.72uH
50
40
30
20
10
0
0
0
5
10
Load Current (A)
15
0
20
Figure 12. Case Temperature Rise vs. Load Current on
4 Layer PCB, 1 oz Copper, 7 cm x 7 cm
1.22
1.22
1.215
1.215
1.21
1.21
1.205
1.2
1.195
1.19
19VIN_1.2VOUT
1.185
12VIN_1.2VOUT
5
10
15
Load Current (A)
20
Figure 13. Case Temperature Rise vs. Load Current
on 4 Layer PCB, 1 oz Copper, 7 cm x 7 cm
Output Voltage (V)
Output Voltage (V)
12VIN_1.2VOUT_1MHz_0.3uH
70
1.205
1.2
1.195
0A_1.2VOUT
1.19
15A_1.2VOUT
1.185
1.18
1.18
0
2
4
6
8
10
7
9
11
13
15
17
19
Load Current (A)
Figure 14. Load Regulation
23
25
Figure 15. Line Regulation
EN (5 V/div)
VIN = 19 V
IOUT = 0 A
21
Input Voltage (V)
EN (5 V/div)
VIN = 19 V
IOUT = 15 A
Soft Start (0.5 V/div)
Soft Start (0.5 V/div)
VOUT (0.5 V/div)
VOUT (0.5 V/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (500 s/div)
Time (500 s/div)
Figure 16. Startup Waveforms with 0 A Load Current
Figure 17. Startup Waveforms with 15 A Load Current
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FAN23SV65AMPX
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Tested using evaluation board circuit shown in Figure 1 with VIN = 19 V, VOUT = 1.2 V, Fsw = 500 kHz, TA = 25°C, and no airflow;
unless otherwise specified.
EN (5 V/div)
EN (5 V/div)
VIN = 19 V
IOUT = 0 A
Soft Start (0.5 V/div)
Soft Start (0.5 V/div)
VIN = 19 V
IOUT = 15 A
VOUT (0.5 V/div)
VOUT Prebias
VOUT (0.5 V/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (200 s/div)
Time (500 s/div)
Figure 18. Shutdown Waveforms with
15 A Load Current
Figure 19. Startup Waveforms with Pre−Bias
Voltage on Output
VOUT (20 mV/div)
VOUT (20 mV/div)
VIN = 19 V
IOUT = 0 A
VIN = 19 V
IOUT = 15 A
VSW (10 V/div)
VSW (10 V/div)
Time (20 s/div)
Time (1 s/div)
Figure 20. Static Load Ripple at No Load
Figure 21. Static Load Ripple at Full Load
VOUT (20 mV/div)
VOUT (20 mV/div)
VIN = 19 V
VOUT = 1.2 V
VIN = 19 V
VOUT = 1.2 V
IOUT (1 A/div)
IOUT (1 A/div)
Time (50 s/div)
Time (50 s/div)
Figure 22. Operation as Load Changes from 0 A to 3 A
Figure 23. Operation as Load Changes from 3 A to 0 A
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FAN23SV65AMPX
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Tested using evaluation board circuit shown in Figure 1 with VIN = 19 V, VOUT = 1.2 V, Fsw = 500 kHz, TA = 25°C, and no airflow;
unless otherwise specified.
VOUT (20 mV/div)
VIN = 19 V, VOUT = 1.2 V
IOUT from 0 A to 7.5 A, 2.5 A/s
VOUT (20 mV/div)
IOUT (5 A/div)
IOUT (5 A/div)
VIN = 19 V, VOUT = 1.2 V
IOUT from 7.5 A, to 15 A, 2.5 A/s
Time (100 s/div)
Time (100 s/div)
Figure 24. Load Transient from 0% to 50%
Load Current
PGOOG (5 V/div)
Figure 25. Load Transient from 50% to 100%
Load Current
PGOOD indicates UVP
With VOUT falling in OCP
Level 2
Vfb (0.5 V/div)
VOUT (1 V/div)
Pull VOUT to 3.8 V
through 3 resistor
Level 1
VOUT (1 V/div)
Soft Start (1 V/div)
PGOOD (5 V/div)
IL (10 A/div)
IOUT = 0 A then short output
VSW (10 V/div)
Time (20 s/div)
Figure 26. Over−Current Protection with Heavy
Load
Figure 27. Over−Voltage Protection Level 1
and Level 2
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FAN23SV65AMPX
CIRCUIT OPERATION
The FAN23SV65A uses a constant on−time modulation
architecture with a VIN feed−forward input to
accommodate a wide VIN range. This method provides
fixed switching frequency (fSW) operation when the
inductor operates in Continuous Conduction Mode (CCM)
and variable frequency when operating in Pulse Frequency
Mode (PFM) at light loads. Additional benefits include
excellent line and load transient response, cycle−by−cycle
current limiting, and no loop compensation is required.
At the beginning of each cycle, FAN23SV65A turns on
the high−side MOSFET (HS) for a fixed duration (tON). At
the end of tON, HS turns off for a duration (tOFF) determined
by the operating conditions. Once the FB voltage (VFB) falls
below the reference voltage (VREF), a new switching cycle
begins.
The modulator provides a minimum off−time (tOFF−MIN)
of 320 ns to provide a guaranteed interval for low−side
MOSFET (LS) current sensing and PFM operation. Toffmin is
also used to provide stability against multiple pulsing and
limits maximum switching frequency during transient
events.
normal operating range. The resistor value can be calculated
from the following equation:
R EN u
V IN,on
V EN,on
Ǔ
*1
(eq. 2)
The FAN23SV65A uses a constant on−time modulation
technique, in which the HS MOSFET is turned on for a fixed
time, set by the modulator, in response to the input voltage
and the frequency setting resistor. This on−time is
proportional to the desired output voltage, divided by the
input voltage. With this proportionality, the frequency is
essentially constant over the load range where inductor
current is continuous.
For buck converter in Continuous−Conduction Mode
(CCM), the switching frequency fSW is expressed as:
f SW +
V OUT
V IN
t ON
(eq. 3)
The on−time generator sets the on−time (tON) for the
high−side MOSFET, which results in the switching
frequency of the regulator during steady−state operation. To
maintain a relatively constant switching frequency over a
wide range of input conditions, the input voltage
information is fed into the on−time generator.
tON is determined by:
The enable pin can be driven with an external logic signal,
connected to a resistive divider from PVIN/Vin to ground to
create an Under−Voltage Lockout (UVLO) based on the
PVIN/VIN supply, or connected to PVIN/VIN through a
single resistor to auto−enable while operating within the EN
pin internal clamp current sink capability.
The EN pin can be directly driven by logic voltages of 5 V,
3.3 V, 2.5 V, etc. If the EN pin is driven by 5 V logic, a small
current flows into the pin when the EN pin voltage exceeds
the internal clamp voltage of 4.3 V. To eliminate clamp
current flowing into the EN pin use a voltage divider to limit
the EN pin voltage to < 4 V.
To implement the UVLO function based on PVIN/VIN
voltage level, select values for R7 and R8 in Figure 1 such
that the tap point reaches 1.26 V when VIN reaches the
desired startup level using the following equation:
ǒ
22 A
Constant On−time Modulation
Enable
R7 + R8
V IN,max * V EN,Clamp,min
t ON +
C tON
I tON
I tON +
1
10
2V
(eq. 4)
V IN
R FREQ
(eq. 5)
where ItON is:
where RFREQ is the frequency−setting resistor described
in the Setting Switching Frequency section; CtON is the
internal 2.2 pF capacitor; and ItON is the VIN feed−forward
current that generates the on−time.
The FAN23SV65A implements open−circuit detection on
the FREQ pin to protect the output from an infinitely long
on−time. In the event the FREQ pin is left floating, switching
of the regulator is disabled. The FAN23SV65A is designed
for VIN input range 7 to 24 V, fSW 200 kHz to 1 MHz,
resulting in an ItON ratio exceeding 1 to 15.
As the ratio of VOUT to VIN increases, tOFF,min introduces
a limit on the maximum switching frequency as calculated
in the following equation, where the factor 1.2 is included in
the denominator to provide some headroom for transient
operation:
(eq. 1)
where VIN,on is the input voltage for startup and VEN,on is
the EN pin rising threshold of 1.26 V. With R8 selected as
10 k, and VIN,on = 9 V the value of R7 is 61.9 k.
The EN pin can be pulled high with a single resistor
connected from VIN to the EN pin. With VIN > 5.5 V a series
resistor is required to limit the current flow into the EN pin
clamp to less than 24 A to keep the internal clamp within
ǒ
V OUT
V in,min
1.2
t OFF,min
1*
f SW +t
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12
Ǔ
(eq. 6)
FAN23SV65AMPX
Soft−Start (SS)
filter of a 10 resistor and 0.1 F capacitor to minimize any
noise sources from the driver supply.
An Under−Voltage Lockout (UVLO) circuit monitors the
VCC voltage to ensure proper operation. Once the VCC voltage
is above the UVLO threshold, the part begins operation after
an initialization routine of 50 s. There is no UVLO circuitry
on either the PVCC or VIN rails.
A conventional soft−start ramp is implemented to provide
a controlled startup sequence of the output voltage. A
current is generated on the SS pin to charge an external
capacitor. The lesser of the voltage on the SS pin and the
reference voltage is used for output regulation.
To reduce VOUT ripple and achieve a smoother ramp of the
output voltage, tON is modulated during soft−start. TON
starts at 50% of the steady−state on−time (PWM Mode) and
ramps up to 100% gradually.
During normal operation, the SS voltage is clamped to
400 mV above the FB voltage. The clamp voltage drops to
40 mV during an overload condition to allow the converter
to recover using the soft−start ramp once the overload
condition is removed. On−time modulation during SS is
disabled when an overload condition exists.
To maintain a monotonic soft−start ramp, the regulator is
forced into PFM Mode during soft−start. The minimum
frequency clamp is disabled during soft−start.
The nominal startup time is programmable through an
internal current source charging the external soft−start
capacitor CSS:
C SS +
I SS
t SS
V REF
Pulse Frequency Modulation (PFM)
One of the key benefits of using a constant on−time
modulation scheme is the seamless transitions in and out of
Pulse Frequency Modulation (PFM) Mode. The PWM
signal is not slave to a fixed oscillator and, therefore, can
operate at any frequency below the target steady−state
frequency. By reducing the frequency during light−load
conditions, the efficiency can be significantly improved.
The FAN23SV65A provides a Zero−Crossing Detector
(ZCD) circuit to identify when the current in the inductor
reverses direction. To improve efficiency at light load, the
LS MOSFET is turned off around the zero crossing to
eliminate negative current in the inductor. For predictable
operation entering PFM mode the controller waits for nine
consecutive zero crossings before allowing the LS
MOSFET to turn off.
In PFM Mode, fSW varies or modulates proportionally to
the load; as load decreases, fSW also decreases. The
switching frequency, while the regulator is operating in
PFM, can be expressed as:
(eq. 7)
where:
CSS = External soft−start programming capacitor;
ISS = Internal soft−start charging current source, 10 A;
tSS = Soft−start time; and
VREF = 600 mV
f SW +
For example; for 1ms startup time, CSS = 15 nF. The
soft−start option can be used for ratiometric tracking. When
EN is LOW, the soft−start capacitor is discharged.
2
t 2ON
L
I OUT
(V IN * V OUT)
V OUT
V IN
(eq. 8)
where L is inductance and IOUT is output load current.
Minimum Frequency Clamp
To maintain a switching frequency above the audible
range, the FAN23SV65A clamps the switching frequency to
a minimum value of 18 kHz. The LS MOSFET is turned on
to discharge the output and trigger a new PWM cycle. The
minimum frequency clamp is disabled during soft−start.
Startup on Pre−Bias
FAN23SV65A allows the regulator to start on a pre−bias
output, VOUT, and ensures VOUT is not discharged during the
soft−start operation.
To guarantee no glitches on VOUT at the beginning of the
soft−start ramp, the LS is disabled until the first
positivegoing edge of the PWM signal. The regulator is also
forced into PFM Mode during soft−start to ensure the
inductor current remains positive, reducing the possibility of
discharging the output voltage.
Protection Features
The converter output is monitored and protected against
over−current,
over−voltage,
under−voltage,
and
hightemperature conditions.
Over−Current Protection (OCP)
The FAN23SV65A uses current information through the
LS to implement valley−current limiting. While an OC
event is detected, the HS is prevented from turning on and
the LS is kept on until the current falls below the
user−defined set point. Once the current is below the set
point, the HS is allowed to turn on.
During an OC event, the output voltage may droop if the
load current is greater than the current the converter is
providing. If the output voltage drops below the UV
threshold, an overload condition is triggered. During an
overload condition, the SS clamp voltage is reduced to
Internal Linear Regulator
The FAN23SV65A includes a linear regulator to facilitate
single−supply operation for self−biased applications. PVCC
is the linear regulator output and supplies power to the
internal gate drivers. The PVCC pin should be bypassed
with a 2. 2 F ceramic capacitor. The device can operate
from a 5 V rail if the VIN, PVIN, and PVCC pins are connected
together to bypass the internal linear regulator.
VCC Bias Supply and UVLO
The VCC rail supplies power to the controller. It is
generally connected to the PVCC rail through a lowpass
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13
FAN23SV65AMPX
40 mV and the on−time is fixed at the steady−state duration.
By nature of the control method; as VOUT drops, the
switching frequency is lower due to the reduced rate of
inductor current decay during the off−time.
The ILIM pin has an open−detection circuit to provide
protection against operation without a current limit.
In certain applications, especially designs utilizing only
ceramic output capacitors, there may not be sufficient ripple
magnitude available on the feedback pin for stable
operation. In this case, an external circuit consisting of 2
resistors (R2 and R6) and 2 capacitors (C4 and C5) can be
added to inject ripple voltage into the FB pin (see Figure 1).
There are some specific considerations when selecting the
RCC ripple injector circuit. For typical applications, use
4.99 k for R6, the value of C4 can be selected as 0.1 F and
approximate values for R2 and C5 can be determined using
the following equations.
R2 must be small enough to develop 12 mV of ripple:
Under−Voltage Protection (UVP)
If VFB is below the under−voltage threshold of −11% VREF
(534 mV), the part enters UVP and PGOOD pulls LOW.
Over−Voltage Protection (OVP)
There are two levels of OV protection: +11% and +22%.
During an OV event, PGOOD pulls LOW.
When VFB is > +11% of VREF (666 mV), both HS and LS
turn off. By turning off the LS during an OV event, VOUT
overshoot can be reduced when there is positive inductor
current by increasing the rate of discharge. Once the VFB
voltage falls below VREF, the latched OV signal is cleared
and operation returns to normal.
A second over−voltage detection is implemented to
protect the load from more serious failure. When VFB rises
+22% above the VREF (732 mV), the HS turns off until a
power cycle on VCC and the LS is forced on until 530 mV
of VFB.
R2 t
(V IN * V OUT) V OUT
V IN 0.012 V C4 f SW
(eq. 11)
R2 must be selected such that the R2C4 time constant
enables stable operation:
R2 t
0.33
2
f SW L OUT
C4
C OUT
(eq. 12)
The minimum value of C5 can be selected to minimize the
capacitive component of ripple appearing on the feedback
pin:
C5 min +
L OUT
R2
C OUT
(R3 ) R4)
R3 R4 C4
(eq. 13)
Using the minimum value of C5 generally offers the best
transient response, and 100 pF is a good initial value in many
applications. However, under some operating conditions
excessive pulse jitter may be observed. To reduce jitter and
improve stability, the value of C5 can be increased:
Over−Temperature Protection (OTP)
FAN23SV65A incorporates an over−temperature
protection circuit that disables the converter when the
controller die temperature reaches 155°C. The IC restarts
when the die temperature falls below 140°C.
C5 ≥ 2
Power Good (PGOOD)
C5 min
(eq. 14)
5 V PVCC
The PGOOD pin serves as an indication to the system that
the output voltage of the regulator is stable and within
regulation. Whenever VOUT is outside the regulation
window or the regulator is at overtemperature (UV, OV, and
OT), the PGOOD pin is pulled LOW.
PGOOD is an open−drain output that asserts LOW when
VOUT is out of regulation or when OT is detected.
The PVCC is the output of the internal regulator that
supplies power to the drivers and VCC. It is crucial to keep
this pin decoupled to PGND with a w1 F X5R or X7R
ceramic capacitor. Because VCC powers internal analog
circuit, it is filtered from PVCC with a 10 resistor and
0.1F X7R decoupling ceramic capacitor to AGND.
Setting the Output Voltage (VOUT)
The output voltage VOUT is regulated by initiating a
highside MOSFET on−time interval when the valley of the
divided output voltage appearing at the FB pin reaches
VREF. Since this method regulates at the valley of the output
ripple voltage, the actual DC output voltage on VOUT is
offset from the programmed output voltage by the average
value of the output ripple voltage. The initial VOUT setting
of the regulator can be programmed from 0.6 V to 5.5 V by
an external resistor divider (R3 and R4):
APPLICATION INFORMATION
Stability
Constant on−time stability consists of two parameters:
stability criterion and sufficient signal at VFB.
Stability criterion is given by:
R ESR
C OUT uu
t ON
2
(eq. 9)
Sufficient signal requirement is given by:
I IND
R ESR u V FB
(eq. 10)
R4 +
where IIND is the inductor current ripple and VFB is the
ripple voltage on VFB, which should be w12 mV.
where VREF is 600 mV.
www.onsemi.com
14
R3
V OUT
*1
V REF
ǒ Ǔ
(eq. 15)
FAN23SV65AMPX
at VIN = 19 V, with a resultant small increase in VIN ripple
voltage above 120 mV used in the calculation. Also, each
10F can carry over 3 ARMS in the frequency range from
100 kHz to 1 MHz, exceeding the input capacitor current
rating requirements. An additional 0.1 F capacitor may be
needed to suppress noise generated by high frequency
switching transitions.
For example; for 1.2 V VOUT and 10 k R3, then R4 is
10 k For 600 mV VOUT, R4 is left open. VFB is trimmed
to a value of 596 mV when VREF = 600 mV, so the final
output voltage, including the effect of the output ripple
voltage, can be approximated by the equation:
ƪ1 ) R3
ƫ ) ƪV2 ƫ
R4
rip
V OUT + V FB
(eq. 16)
Output Capacitor Selection
Output capacitor COUT is selected based on voltage rating,
RMS current ICOUT(RMS) rating, and capacitance. For
capacitors having DC voltage bias derating, such as ceramic
capacitors, higher rating is highly recommended.
When calculating COUT, usually the dominant
requirement is the current load step transient. If the
unloading transient requirement (IOUT transitioning from
HIGH to LOW), is satisfied, then the load transient (IOUT
transitioning LOW to HIGH), is also usually satisfied. The
unloading COUT calculation, assuming COUT has negligible
parasitic resistance and inductance in the circuit path, is
given by:
Setting the Switching Frequency (fSW)
fSW is programmed through external RFREQ as follows:
R FREQ +
V OUT
V tON
20
f SW
(eq. 17)
where CtON = 2.2 pF internal capacitor that generates tON.
For example; for fSW = 500 kHz and VOUT = 1.2 V, select a
standard value for RFREQ = 54.9 k.
Inductor Selection
The inductor is typically selected based on the ripple
current (IL), which is usually selected as 25% to 45% of the
maximum DC load. The inductor current rating should be
selected such that the saturation and heating current ratings
exceed the intended currents encountered in the application
over the expected temperature range of operation.
Regulators that require fast transient response use smaller
inductance and higher current ripple; while regulators that
require higher efficiency keep ripple current on the low side.
The inductor value is given by:
L+
(V IN * V OUT)
I L
f SW
V OUT
V IN
C OUT + L
(eq. 18)
Input Capacitor Selection
Setting the Current Limit
Input capacitor CIN is selected based on voltage rating,
RMS current ICIN(RMS) rating, and capacitance. For
capacitors having DC voltage bias derating, such as ceramic
capacitors, higher rating is strongly recommended. RMS
current rating is given by:
ǸD (1 * D) (eq. 19)
I CIN(RMS) + I LOAD*MAX
Current limit is implemented by sensing the inductor
valley current across the LS MOSFET VDS during the LS
on−time. The current limit comparator prevents a new
on−time from being started until the valley current is less
than the current limit.
The set point is configured by connecting a resistor from
the ILIM pin to the SW pin. A trimmed current is output onto
the ILIM pin, which creates a voltage across the resistor.
When the voltage on ILIM goes negative, an over−current
condition is detected.
RILIM is calculated by:
where ILOAD−MAX is the maximum load current and D is
the duty cycle VOUT/VIN. The maximum ICIN(RMS) occurs
at 50% duty cycle.
The capacitance is given by:
I LOAD*MAX
f SW
D (1 * D)
V IN
(eq. 21)
where IMAX and IMIN are maximum and minimum load
steps, respectively and VOUT is the voltage overshoot,
usually specified at 3 to 5%.
For example: for VI = 12 V, VOUT = 1.2 V, 10 A IMAX, 5 A
IMIN, fSW = 500 kHz, LOUT = 560 nH, and 4% VOUT
deviation of 48 mV; the COUT value is calculated to be 356 F.
This capacitor requirement can be satisfied using eight
47F, 6.3 V−rated X5R ceramic capacitors. This
calculation applies for load current slew rates that are faster
than the inductor current slew rate, which can be defined as
VOUT/L during the load current removal.
For example: for 19 V VIN, 1.2 V VOUT, 15 A load, 25%
IL, and 500 kHz fSW; L is 576 nH, and a standard value of
560 nH is selected.
C IN +
I 2MAX * I 2MIN
(V OUT ) V OUT) 2 * V 2OUT
(eq. 20)
R ILIM + 1.08
where VIN is the input voltage ripple, normally 1% of
VIN.
For example; for VIN = 19 V, VIN = 120 mV, VOUT =
1.2 V, 15 A load, and fSW = 500 kHz; CIN is 14.8 F and
ICIN(RMS) is 3.64 ARMS. Select a minimum of three 10 F 25
V rated ceramic capacitors with X7R or similar dielectric,
recognizing that the capacitor DC bias characteristic
indicates that the capacitance value falls approximately 60%
K ILIM
I VALLEY
(eq. 22)
where KILIM is the current source scale factor, and
IVALLEY is the inductor valley current when the current limit
threshold is reached. The factor 1.08 accounts for the
temperature offset of the LS MOSFET compared to the
control circuit.
With the constant on−time architecture, HS is always
turned on for a fixed on−time; this determines the
peak−to−peak inductor current.
www.onsemi.com
15
FAN23SV65AMPX
Current ripple I is given by:
I L +
ǒV IN * VOUTǓ
t ON
L
Sensitive analog components including SS, FB, ILIM,
FREQ, and EN should be placed away from the highvoltage
switching circuits such as SW and BOOT and connected to
their respective pins with short traces. The inner PCB layer
closest to the FAN23SV65A device should have power
ground (PGND) under the power processing portion of the
device (PVIN, SW, and PGND). This inner PCB layer
should have a separate analog ground (AGND) under the P1
pad and the associated analog components. AGND and
PGND should be connected together near the IC between
PGND pins 18−21 and AGND pin 23, which connects to P1
thermal pad.
The AGND thermal pad (P1) should be connected to
AGND plane on inner layer using four 0.25 mm vias spread
under the pad. No vias are included under PVIN (P2) and
SW (P3) to maintain the PGND plane under the power
circuitry intact.
Power circuit loops that carry high currents should be
arranged to minimize the loop area. Primary focus should be
to minimize the loop for current flow from the input
capacitor to PVIN, through the internal MOSFETs, and
returning to the input capacitor. The input capacitor should
be as close to the PVIN terminals as possible.
The current return path from PGND at the low−side
MOSFET source to the negative terminal of the input
capacitor can be routed under the inductor and also through
vias that connect the input capacitor and lowside MOSFET
source to the PGND region under the power portion of the
IC.
The SW node trace that connects the source of the
high−side MOSFET and the drain of the low−side MOSFET
to the inductor should be short and wide.
To control the voltage across the output capacitor, the
output voltage divider should be located close to the FB pin,
with the upper FB voltage divider resistor connected to the
positive side of the output capacitor and the bottom resistor
connected to the AGND portion of the FAN23SV65A
device.
When using ceramic capacitors with external ramp
injection circuitry (R2, C4, C5 in Figure 1), R2 and C4
should be connected near the inductor and coupling
capacitor C5 should be placed near FB pin to minimize FB
pin trace length.
Decoupling capacitors for PVCC and VCC should be
located close to their respective device pins.
SW node connections to BOOT, ILIM, and ripple
injection resistor R2 should be through separate traces.
(eq. 23)
From the equation above, the worst−case ripple occurs
during an output short circuit (where VOUT is 0 V). This
should be taken into account when selecting the current limit
set point.
The FAN23SV15M uses valley−current sensing; the
current limit (IILIM) set point is the valley (IVALLEY).
The valley current level for calculating RILIM is given by:
I VALLEY + I LOAD(CL) *
I L
2
(eq. 24)
where ILOAD (CL) is the DC load current when the current
limit threshold is reached.
For example: In a converter designed for 15 A steadystate
operation and 4.5 A current ripple, the current−limit
threshold could be selected at 120% of ILOAD,(SS) to
accommodate transient operation and inductor value
decrease under loading. As a result, ILOAD,(CL) is 18 A,
IVALLEY = 15.75 A, and RILIM is selected as the standard
value of 1.47 k.
Boot Resistor
In some applications, especially with higher input
voltage, the VSW ring voltage may exceed derating
guidelines of 80% to 90% of absolute rating for VSW. In this
situation a resistor can be connected in series with boot
capacitor (C3 in Figure 1) to reduce the turn−on speed of the
high side MOSFET to reduce the amplitude of the VSW ring
voltage. If necessary, a resistor and capacitor snubber can be
added from VSW to PGND to reduce the magnitude of the
ringing voltage. Please contact ON Semiconductor
Customer Support for assistance selecting a boot resistor or
snubber circuit in applications that operate above a 21 V
typical input voltage.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
GUIDELINES
The following points should be considered before
beginning a PCB layout using the FAN23SV65A. A sample
PCB layout from the evaluation board is shown in Figure 28
− Figure 31 following these layout guidelines.
Power components (input capacitors, output capacitors,
inductor, and FAN23SV65A device) should be placed on a
common side of the PCB in close proximity to each other
and connected using surface copper.
www.onsemi.com
16
FAN23SV65AMPX
Figure 28. Evaluation Board Top Layer Copper
Figure 29. Evaluation Board Inner Layer 1 Copper
www.onsemi.com
17
FAN23SV65AMPX
Figure 30. Evaluation Board Top Layer Copper
Figure 31. Evaluation Board Inner Layer 1 Copper
www.onsemi.com
18
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN34 5X5.5, 0.5P
CASE 483AM
ISSUE A
DOCUMENT NUMBER:
DESCRIPTION:
98AON13662G
PQFN34 5X5.5, 0.5P
DATE 02 JUL 2021
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN34 5X5.5, 0.5P
CASE 483AM
ISSUE A
DOCUMENT NUMBER:
DESCRIPTION:
98AON13662G
PQFN34 5X5.5, 0.5P
DATE 02 JUL 2021
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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